[New 20 September 2006]

The Emulation Baseboard (EB) user guide and application note AN152 do not correctly explain interrupt routing with the ARM11 MPCore Core Tile. The tables below show the correct interrupt routing into the pins on the MPCore test chip. This information applies to the EB FPGA image provided in AN152 version C1.

AN152 supports three interrupt modes, and you can enable the nFIQ interrupts for each mode. These modes are selected using the INTMODE[2:0] field in the EB's SYS_PLD_CTL1 register. To configure interrupts you must also write to other registers in the EB and MPCore.

You should refer to the EB user guide and AN152 for other details.

Legacy mode

This mode supports the MPCore 'legacy ARM interrupts' mode, which uses the legacy nIRQ pins instead of the MPCore's Interrupt Distributor. This mode is the default and is used to run the boot monitor on CPU 0. To select this mode set INTMODE[2:0] = X00, where X=1 enables or  X=0 disables the nFIQ inputs.

* if FIQs enabled using INTMODE2 = 1, otherwise the nFIQ is logic 1

† these DCC interrupts are input to the EB FPGA but not used

‡ not used by the MPCore in legacy ARM interrupts mode

New mode with DCC

New mode uses the MPCore's Interrupt Distributor and DCC stands for 'Debug Communications Channel'. DCC enables you to communicate with your application using JTAG, without stopping the processor. To select this mode set INTMODE[2:0] = X01, where X=1 enables or X=0 disables the nFIQ inputs.

* if FIQs enabled using INTMODE2 = 1, otherwise the nFIQ is logic 1

† the MPCore Interrupt Distributor presents these as INT31

New mode without DCC

This mode uses the MPCore's Interrupt Distributor. We recommend you use this mode for symmetric multi-processing (SMP) to get the maximum benefit from the MPCore. To select this mode set INTMODE[2:0] = X10, where X=1 enables or X=0 disables the nFIQ inputs.

* if FIQs enabled using INTMODE2 = 1, otherwise the nFIQ is logic 1