There is a design issue in the Versatile PB926EJ-S revision C baseboard JTAG circuit.  This is only a problem when loading the Logic Tile FPGA configuration flash when there is a Core Tile mounted on top of the Logic Tile.  When in debug mode, the JTAG system and connection to a debugger will work correctly.

Newer (lead free boards) revision D do not have this issue.  The revision of the board can be found in the corner by the character LCD.  For example, the revision C board is labelled HBI-0117C.

The symptoms are:

• If using progcards_multiice, the Multi-ICE server will fail to auto-configure.
• If using progcards_rvi, it will report that auto-detection has failed.
• If using progcards_usb you will get the error 'found too many devices:. XXX'.

The only work-around for this is to remove the Core Tile, perform the programming, then re-fit the Core Tile.

Detailed description of design issue:

When the PB926EJ-S baseboard is in configuration mode, the signal D_RTCK is set to high impedance by any Logic Tiles connected. Core Tiles do not tri-state this signal.  On the baseboard, the D_RTCK signal should be isolated from the SDC_TCK (TCK to the ARM926EJ-S development chip) when in configuration mode, but this function is missing in the revision C PCB, and causes the JTAG communication to fail.