All components of RVDS 2.x and later support the ARM v6 Architecture. The compiler can generate some v6 instructions, the assembler accepts all v6 instructions, the linker will link in v6 library objects where required, and fromelf will disassemble the v6 instructions correctly. The compiler's "inline assembler" supports some of the v6 instructions and the "embedded assembler" supports all of the v6 instructions.

To enable architecture v6 support for compiled code, compile with, for example:

• --cpu 6 (For generic v6 support)
• --cpu ARM1136J-S (To generate code specifically for the ARM1136J-S)
• --cpu ARM1136JF-S (To generate code specifically for the ARM1136JF-S, which includes the VFP hardware floating point)

Instruction generation

When compiling code for architecture v6, the compiler will generate the new sign-extend and zero-extend instructions (for example, SXTB), where appropriate (see Example 1 below). Code scheduling for ARM11 cores is performed. The compiler cannot generate the new SIMD instructions, as these do not map well onto C expressions. The RVCT 2.0 compiler cannot generate the endian reversal instructions (REV, REV16 and REVSH), but the RVCT 2.1 and newer compilers will generate these if they can deduce that a C expression performs an endian reversal. In addition the C libraries contain some v6 specific implementations of C-library functions such as memcpy. RVCT 2.2 and later additionally support Thumb-2 code generation for the ARM1156T2-S.

Alignment Support

The compiler will utilize v6 unaligned access support by default to speed up access to packed structures, by allowing an LDR (or STR) to load from (or store to) a non-word aligned address (see Example 2 below). Note that code compiled using the default options for architecture v6 will only run correctly if unaligned support is enabled on the ARM core (U=1, A=0 in CP15 register 1). Unaligned accesses can alternatively be enabled from reset by tying the UBITINIT input to the core HIGH.

Remember that the compiler will not misalign data by default and the use of unaligned data remains under your explicit control. Structures and other objects remain naturally aligned unless explicitly qualified with __packed.  Using __packed for unaligned pointers also indicates to the compiler that it cannot use LDM/STM/LDRD/STRD.

In some circumstances you may wish to use the legacy (pre-v6) alignment mode (U=0, A=0 in CP15 register 1), where unaligned loads will rotate the loaded value. The only support in RVCT for this mode of operation is to compile using --cpu 5TE. Please be aware that this means your compiled code will not use any architecture v6 instructions.

Modulo eight alignment checking without unaligned accesses (U=0, A=1 in CP15 register 1) is not supported by the tools.

If a v6 target is to be used with modulo 4 alignment checking enabled (U=1, A=1 in CP15 register 1), your code should be compiled and assembled with the appropriate option:

• --memaccess -UL41  for RVCT 2.x
• --no_unaligned_access  for RVCT 3.x

Note that the --memaccess switch is deprecated in RVCT 3.0 and will be removed in a future release of the tools.

Endian Support

The ARM compiler has options for producing either little endian or big endian objects.

ARM Architecture v6 introduces two different big endian modes BE8 (new) and BE32 (legacy).

When compiling for v6 big endian, the ARM compiler will normally generate big endian objects as BE8 rather BE32. A flag is set in the object code which labels the code as BE8. Therefore, you will normally need to enable BE8 support in the ARM core by setting the E-bit in the CPSR.

You can link legacy (e.g v4T) objects with new v6 objects (for running on v6), but in this case the linker will switch the byte order of the legacy object code into BE8 mode. The resulting image is BE8.

If you wish to use the legacy BE32 mode, then you will need to tie the BIGENDINIT input into the core HIGH, or set the B bit (bit 7) of CP15 register 1 in your initialisation code.

BE32-compatible code can then be generated by using the compiler option:
--memaccess -UL41 or --no_unaligned_access as above.

BE32-compatible code will also need to be linked using the "armlink --be32" option, as otherwise the v6 attribute of the objects will cause a BE8 image to be produced.

Example 1

signed char unpack(int i)
{
    return (signed char)i;
}

Compiled for --cpu 5 gives:

unpack PROC
       MOV      r0,r0,LSL #24
       MOV      r0,r0,ASR #24
       BX       lr
       ENDP

Compiled for --cpu 6 gives:

unpack PROC
       SEXT8    r0,r0
       BX       lr
       ENDP

Note that the ARM instruction "SEXT8" was formerly known as "SUNPK8TO32".

The disassembly view from RVCT 2.2 and later may look slightly different, due to the new Unified Assembler notation.  For more information on these differences please consult section 2.11 of the RVCT 2.2 or 3.x Assembler Guide.

Example2

__packed struct
{
    char ch;
    short sh;
    int i;
} foo;

signed char unpack()
{
    return (signed char)foo.i;
}

Compiled for --cpu 5 gives:

unpack PROC
       STMFD    sp!,{r3,lr}
       LDR      r0,|L1.24|
       BL       __rt_uread4
       MOV      r0,r0,LSL #24
       MOV      r0,r0,ASR #24
       LDMFD    sp!,{r3,pc}
|L1.24|
       DCD      ||.bss$2|| + 3
       ENDP

Compiled for --cpu 6 gives:

unpack PROC
       LDR      r0,|L1.16|
       LDR      r0,[r0,#3]
       SEXT8    r0,r0
       BX       lr
|L1.16|
       DCD      ||.bss$2||
       ENDP