[updated 3 April 2007]

Many customers want to increase the performance of ARM development boards to be nearer their final ASIC. For example, the ARM1136JF-S core was designed to run at 330-550MHz, but the test chip on our boards runs at a default 240MHz. Please note that we cannot guarantee the maximum operating frequency of our boards, there will be some variation between boards, and you may only be able to achieve a relatively small increase, for example to 285MHz.

Some customers want to reduce clock speeds for benchmarking or to prototype their hardware in an FPGA. The minimum AHB bus frequency is 25MHz, due to the delay locked loop (DLL) used in the FPGA.

We have written application note AN174 to cover the details not provided in the CM1136JF-S user guide about changing the clocks. AN174 describes the clock circuits, gives step-by-step instructions how to change the frequencies, and includes programs to set and measure the clocks. The program to set the clocks assumes you have an Integrator/CP baseboard; it does not work with an Integrator/AP or no baseboard.