The test chips used on the CT926EJ-S Core Tile have an internal interrupt controller, which sits between the test chip nIRQ and nFIQ pins and the corresponding interrupt inputs on the ARM core itself. To enable interrupts on these test chips you must either:

• Tie the USERIN[3] signal of the Core Tile LOW, which bypasses the internal interrupt controller and connects the test chip nIRQ and nFIQ signals directly to the ARM core. USERIN[3] is pin 18 on the HDRX header connectors, and has the generic names XU/XL[81]

or

• Enable the internal interrupt controller and program it in an appropriate manner. The example FPGA logic in Applications Note 125 enables this interrupt controller, and the accompanying PDF document and example software describes how to program it.

If you have RealView Debugger (RVD) then you can use 'vector_catch' in the RVD register window to trap the IRQ and FIQ exceptions. You must also have interrupts enabled in the CPSR (Current Program Status Register) in the ARM core.