This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.
ARM websites use two types of cookie: (1) those that enable the site to function and perform as required; and (2) analytical cookies which anonymously track visitors only while using the site. If you are not happy with this use of these cookies please review our Privacy Policy to learn how they can be disabled. By disabling cookies some features of the site will not work.
This course is for engineers who will integrate the Cortex-R7MPcore in to an SoC design. It assumes no knowledge of ARM processors or associated bus protocols. It starts by introducing the essential ideas of the ARM architecture, micro-architecure and bus protocols. It then looks at the main blocks and behaviours of the C-R7MPcore. It also introduces CoreSight debug infrastructure and the embedded debug features of the C-R7 processors.
Prerequisites:
Some knowledge of embedded systems
Familiarity with digital logic and hardware/ASIC design issues
A basic awareness of ARM is useful but not essential
Audience:
Hardware design engineers who need to understand the issues involved when designing SoC's around the ARM Cortex-R7 processor core.
Modules:
The ARM Architecture
ARM v4T
ARM v6
ARM v7-R
Thumb and Thumb-2
ARM v6 Memory Types
PMSA-v6/7
Exception Handling
CPU Architectures
Memory Sub-Systems
Introduction to SMP & MESI
AXI Protocol
AXI Interconnection Architectures
NIC301
AMBA Designer
APB
Cortex-R7 MPCore Overview
Cortex-R7 Processor Core
Cortex-R7 L1 Sub-Systems
Cortex-R7 MPCore Sub-Systems
Cortex-R7 MPCore L2 Interfaces
Cortex-R7 Fault Tolerance Support
Cortex-R7 MPCore Configuration & Deployment
Cortex-R7 MPCore Implementation Overview
Cortex-R7 MPCore Clocks, Resets & Power Managament