Chinese

Japanese

About ARM

Forums

Events

News

Employment

Investors

	MARKETS		PRODUCTS & SOLUTIONS		CONNECTED COMMUNITY		TECHNICAL SUPPORT		DOCUMENTATION


		Technical Support


		Home Page

		Obtaining Support

		FAQs


		Development Tool FAQs


		IP FAQs


		Embedded Software FAQs


		Artisan Physical IP FAQs (Login Required)


		Downloads

		Documentation

		Training

		Where To Buy

		Keil MCU Tools

		What's New

		ARM Newsgroups

		Active Assist On-site Services




(Advanced Search) FAQs Documentation Downloads Forums

Cores - Cache and Write Buffer

To find information on a particular product, simply expand the relevant section.
To expand/collapse all products simply click on the appropriate button below:

For further information you can use our 'Technical Support Search' facility at the bottom of this page.

ARM1020/22E

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

ARM1026EJ-S

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

ARM1136

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

ARM1156

Can I hook up my ARM1176 to a L2 cache ?

ARM1176

Can I hook up my ARM1176 to a L2 cache ?

ARM720T (Rev 0-3)

Can a piece of code be locked into the cache?

Does the ARM720T with the cache disabled behave like an ARM7TDMI?

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

In the ARM720 Technical Reference Manual chapter, it is stated that the write buffer can hold up to 8 words of data and 4 independent addresses. Why is this?

Is the cache in ARM720T a write through cache or a write back one?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

What does the ARM720T do when the cache is not enabled?

What will happen on a write-miss to a cacheable location?

Which cached cores are available and what do they include?

ARM720T (Rev 4)

Can a piece of code be locked into the cache?

Is the cache in ARM720T a write through cache or a write back one?

What will happen on a write-miss to a cacheable location?

ARM920/922T

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

ARM926EJ-S

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

What cache sizes can be used in the ARM926EJ-S Macrocell?

Which cached cores are available and what do they include?

ARM940T

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

ARM946E-S

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

ARM966E-S

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

To download a single page of Cores - Cache and Write Buffer FAQs specific to the Product(s) you are interested in, please click on the 'Merge FAQs' button below. On the page that follows you will be prompted to select which Product(s) you wish to be included in your customized list of FAQs.

Back to FAQs index

Other ARM Websites

Glossary | Sitemap | Help

LEGAL STATEMENT