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ARM920/922T

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Cores

How do I lockdown part of my data cache?

What are the timing requirements of interrupts entering the ARM core?

Cores - Bus Interface

Are there are any special considerations when memory mapping hardware registers?

How does Little / Big Endian mode affect aligned / unaligned addressing?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

What is the difference between a von Neumann architecture and a Harvard architecture?

Cores - Cache and Write Buffer

If the write buffer is full and the ARM wants to perform another write, will it stall the processor?

Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?

Which cached cores are available and what do they include?

Cores - Clocking

What are the considerations when designing with an ARM hard macro clock?

Cores - Coprocessor

I'm not implementing an external coprocessor. How should I tie off the interface?

Cores - Debug

How do I add scan chains to the ARM TAP controller?

In which direction do the debug scan chains scan?

We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?

What do I set the ARM TAP IDCODE to?

What is the timing relationship between TDI/SDIN and TDO/SDOUTBS?

Cores - Interrupts

Are the IRQ and FIQ interrupts level-sensitive?

What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?

Cores - MMU/MPU

Which cached cores are available and what do they include?

Cores - Reset and Initialization

Do I need to keep the clock running when the reset line is asserted?

How can the ARM banked registers be initialized?

What values are in ARM registers after a power-on reset?

Cores - Test

During AMBA test some signals toggle unpredictably. Why is this?

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