Breaking Through the Software-Hardware Debug Barrier
ARM Development Studio 5 (DS-5™) Altera Edition toolchain is the result of the partnership between ARM and Altera to create of an adaptive, customized software development environment for Altera SoC FPGA devices. Part of the Altera SoC Embedded Design Suite, ARM DS-5 Altera Edition takes advantage of the high-bandwidth interconnect backbone between the dual ARM® Cortex™-A9 hard processor system (HPS) and the Cyclone® V or Arria® V FPGA fabric to eliminate the barrier that separates hardware and software debug in complex embedded systems. The integration of these two domains in a single development solution accelerates the entire design flow by giving engineers more control and visibility across the system. Learn more about ARM DS-5 support for Altera SoC FPGAs...
Software Debug Via USB Blaster
In addition to ARM's high performance DSTREAM debug and trace connection, Altera SoC FPGA customers have the option to use the Altera USB Blaster JTAG to gain run-control debug access to the Cortex-A9 HPS via the DS-5 Debugger. This integration provides a cost efficient JTAG connection solution for DS-5 and also other Altera JTAG-based tools.
Compare Editions
| Altera Edition | Professional Edition | ||
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| IDE | |||
| DS-5 Eclipse IDE |
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| Code Generation | |||
| ARM Compiler |
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| GNU Compiler for Linux |
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| Target Connection | |||
| Targets | Altera SoC FPGA devices | See list | |
| Debug Connection | See list | ||
| Debug & Optimization | |||
| Streamline System Analysis |
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| Run-Control (JTAG) Multicore Debug |
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| ETM and PTM Instruction Trace |
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| ITM and STM Instrumentation Trace |
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| Simulation | |||
| Cortex-A8 VE Virtual Platform |
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| Quad Cortex-A9 VE Virtual Platform |
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| Altera SoC FPGA Virtual Target |
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| Commercial | |||
| Node Locked / Floating | NL | NL and FL | |
| Support & Maintenance | Altera | ARM and | |
| Availability | Early 2013 |
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