(View Larger ARM VSTREAM Virtual Debug Interface Image)
VSTREAM enables the stop-mode debug features usually available in professional debug adaptors including stopping the processor, view and change the value of processor registers and system memory and single-step through code. However, this is not done via a physical JTAG connection, but via SCE-MI2 or ZEMI-3 transactors directly into the SoC RTL. Not only this virtual connection is much faster, but it is also easier to start remotely, not requiring any modification to the emulator hardware set-up.
VSTREAM can also capture trace from a TPIU output in a similar manner.
The ARM DS-5 suite is the ideal companion to VSTREAM; used together they can help verify the correct implementation of the debug and trace fabric of the SoC, including any CoreSight components, by running high-level test patterns and connecting an actual debugger to the RTL simulator. The connection of the processor to the memory system and memory-mapped peripherals can be easily validated by opening memory views in the debugger. Instead of finding problems with a design's debug architecture after tape-out they can now be found in the RTL.
VSTREAM supports post-process PTM™ and ETM™ instruction trace after a simulation run in order to get a history of instructions executed by the processor in a non-intrusive way.
VSTREAM enables more efficient software development in the early stages of system design, improving the utilization of hardware emulators and reducing project risk and time-to-market.It also helps in proving the integration of SoC components by running functional test software including boot code on RTL simulators.
