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Altera SoC FPGA

Altera logoHighly Integrated ARM® Cortex-A9 HPS and FPGA

The Altera SoC FPGAs integrate a dual ARM Cortex-A9 hard processor system (HPS) with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of ASICs with the flexibility of programmable logic. These devices join the diverse family of Cyclone® V and Arria® V FPGAs and include additional hard logic such as PCI Express® Gen2, multiport memory controllers, and high-speed serial transceivers 

Altera SoC FPGA

HPS-FPGA Cross-Domain Debug

The interconnection between the HPS and FPGA fabric in the Altera SoC FPGAs is explored by the ARM DS-5toolchain to give software engineers unprecedented visibility and control across the two domains. A few examples of what is possible to do using the integrated software-hardware debug in DS-5 for Altera SoC FPGA devices:

  • Qsys-generated FPGA peripheral registers definition can be imported into DS-5 Debugger for system register visibility while debugging software
  • Cross-triggering between the HPS and FPGA fabric allows inter-domain synchronization, for instance, to stop all hard and soft processors simultaneously.
  • Timestamped processor (PTM) and system trace (STM) streams for correlation of processor execution flow with system events

Altera USB Blaster II Support

Altera USB Blaster II cableIn addition to ARM's high performance DSTREAM debug and trace connection, Altera SoC FPGA customers have the option to use the Altera USB Blaster JTAG to gain run-control debug access to the Cortex-A9 HPS via the DS-5 Debugger. This integration provides a cost efficient JTAG connection solution for DS-5 and also other Altera JTAG-based tools.

 

ARM DS-5 Altera Edition

DS-5 Altera Edition is the result of the partnership between ARM and Altera to create of a targeted software development environment for Altera SoC FPGA devices at lower price point than DS-5 Professional Edition. Part of the Altera SoC Embedded Design Suite, ARM DS-5 Altera Edition can be used for debug and optimization of designs based on the Altera SoC FPGAs. Find out more.