Developers can use Juno boards for early access of porting OS kernel or driver code to the big.LITTLE architecture, based on the Cortex-A72 or Cortex-A57 and Cortex-A53 ARM v8 processors or PCI-Express development.
The table below outlines the difference between the Juno variants
|Juno r0||Juno r1||Juno r2|
|Target application||Platform for big.LITTLE development with ARMv8-A||Platform for PCI-Express development with ARMv8-A||Platform for big.LITTLE development with big.LITTLE and PCI-Express|
|big cluster||Cortex-A57 r0p0||Cortex-A57 r0p1||Cortex-A72 r0p0eac|
|LITTLE cluster||Cortex-A53 r0p0||Cortex-A53 r0p3||Cortex-A53 r0p3|
|STM||STM r0p1||STM-500 r0p1||STM-500 r0p1|
|FPGA support||IO coherent||Fully coherent||Fully coherent|
|PCI-Express support||No||Yes, 4 lanes plus GbEthernet & SATA||Yes, 4 lanes plus GbEthernet & SATA|
Juno Platforms can also be expanded by adding a LogicTile Express board to the tile site on the motherboard. This adds a large FPGA for prototyping custom logic blocks alongside the ARM processor. The exported AXI interface from the platform has dedicated routing, directly linking the Test Chip and FPGA. This ensures sufficent bandwidth is available for the user AXI subsystem. To enable early access to hardware the TestChip has not been fully optimized for performance and power.
A microcontroller-based configuration mechanism provides an easy, USB-based plug-and-play method for programming software, firmware and FPGA images into the system flash memory from an attached PC.
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