Developers can use Juno boards for early access of porting OS kernel or driver code to the big.LITTLE architecture, based on the Cortex-A57 and Cortex-A53 ARM v8 processors or PCI-Express development.
The Juno r1 variant which has a 4 lane Gen 2.0 PCI-Express root port it is aimed at PCI-Express development with ARMv8-A. This version of Juno does not support the big.LITTLE MP Global Task Scheduling model.
Juno Platforms can also be expanded by adding a LogicTile Express board to the tile site on the motherboard. This adds a large FPGA for prototyping custom logic blocks alongside the ARM processor. The exported AXI interface from the platform has dedicated routing, directly linking the Test Chip and FPGA. This ensures sufficent bandwidth is available for the user AXI subsystem. To enable early access to hardware the TestChip has not been fully optimized for performance and power.
A microcontroller-based configuration mechanism provides an easy, USB-based plug-and-play method for programming software, firmware and FPGA images into the system flash memory from an attached PC.