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Juno ARM Development Platform

Juno ARM Development Platform Image (View Larger Juno ARM Development Platform Image)
The Juno ARM Development Platform is a software development platform for ARMv8-A, it includes the Juno Versatile Express board and an ARMv8-A reference software port available through Linaro. The Juno hardware delivers to software developers an open, vendor neutral ARMv8 development platform with :
  • ARM® Cortex®-A57 and Cortex-A53 MPCore for ARMv8 big.LITTLE
  • Mali-T624 for 3D Graphics Acceleration and GP-GPU compute
  • 4 lane Gen 2.0 PCI-Express (Juno r1 only)
  • A SoC architecture aligned with Level 1 (Server) Base System Architecture

The Juno software stack available through Linaro delivers to developers an out-of-the-box Linux software package running:

  • ARM Trusted Firmware
  • A 64-bit Linux Kernel with big.LITTLE and Mali support
  • Linux based file systems
  • It enables:
  • ARMv8-A AArch64 kernel and tools development for Cortex-A50 processor family 
  • PCI-Express software development (Juno r1 only)
  • Secure OS & Hypervisors through ARM Trusted Firmware
  • Expansion using a LogicTile Express 20MG FPGA board that connects directly to the platform
  • 3D graphics and GPU compute with native big.LITTLE and Mali support
  • Middleware & file systems porting and optimisation to 64-bit
  • Real-time debug, trace and performance tuning with CoreSight technology

The Juno ARM Connected Community page contains information on Juno setup and configuration and a number of FAQs.

 

 

The ARM® Versatile Express family of development boards provide an excellent environment for development of the next generation of system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged.

Developers can use Juno boards for early access of porting OS kernel or driver code to the big.LITTLE architecture, based on the Cortex-A57 and Cortex-A53 ARM v8 processors or PCI-Express development.

The Juno r1 variant which has a 4 lane Gen 2.0 PCI-Express root port it is aimed at PCI-Express development with ARMv8-A. This version of Juno does not support the big.LITTLE MP Global Task Scheduling model.

Juno Platforms can also be expanded by adding a LogicTile Express board to the tile site on the motherboard. This adds a large FPGA for prototyping custom logic blocks alongside the ARM processor. The exported AXI interface from the platform has dedicated routing, directly linking the Test Chip and FPGA. This ensures sufficent bandwidth is available for the user AXI subsystem. To enable early access to hardware the TestChip has not been fully optimized for performance and power.

A microcontroller-based configuration mechanism provides an easy, USB-based plug-and-play method for programming software, firmware and FPGA images into the system flash memory from an attached PC.

 
 


 

 

  • System Control Processor (SCP) Firmware
    • System initialisation, cold boot flow and controls clocks, voltage, power gating.
    • ARMv7-M architecture, thumb2 AArch32 instruction set 
  • Application Processor (AP) Trusted Firmware
    • Sets up security and virtualization
    • Loads subsequent boot stages
    • EL3 monitor layer
    • PSCI support (a power management API to do shutdown/wakeup operations as well as other features)
    • Standardised APIs (SCPI, PSCI)
    • AArch64 Executable binaries and partially as source code
  • EDK2 (an open source implementation of UEFI)
    • Supports USB and network boot
    • Loads the Rich Operating System (OS)
    • Standardised APIs and easy to extend
    • AArch64 source code
  • Android
    • Unified kernel. The same kernel binary can boot Linux or Android
    • Android Open Source Project (AOSP) 32-bit filesystem from Linaro
    • Android LSK available here
  • A Linaro Evaluation Build (LEB) of the Linux kernel
    • Demonstrates Linux running
    • 64-bit kernel that can mount a 32-bit or 64-bit filesystem
    • Combines all the Juno software components required to boot Linux on Juno
    • Mali kernel driver and user space driver
    • Power management and scheduler optimizations
    • Linux device drivers for all supported Juno I/O
    • Unified Linux/Android kernel. The same kernel binary can boot either Linux or AOSP
    • AArch64 Executable binaries and source code
    • Open embedded LSK available here

 

 

 

 

The Juno ARM Development Platform has the following features

  • Compute Subsystem
    • Dual Cluster, big.LITTLE configuration
    • Cortex-A57 MP2 cluster (r0p0)
      • Caches: L1 48KB I, 32KB D, L2 2MB
    • Cortex-A53 MP4 cluster (r0p0)
      • Caches: L1 32KB, L2 1MB
    • Quad Core MALI T624 r1p0
      • Caches: L2 128KB
    • CoreSight ETM/CTI per core & STM-500 (Juno r1 only)
    • DVFS and power gating via SCP
    • 4 energy meters
    • DMC-400 dual channel (2x32bit) DDR3L interface, 8GB 800MHz (1600MT/s)
    • Internal CCI-400, 128-bit, 533MHz
  • Rest of SoC
    • Internal NIC-400, 64-bit, 400MHz
    • External AXI ports: using Thin- Links
    • DMAC : PL330, 128-bit
    • Static Memory Bus Interface : PL354
      • 32bit 50MHz to slow speed peripheral
    • HDCLD dual video controllers: 1080p
  • Expansion support
    • AXI expansion to FPGA daughterboard
    • USB 2.0 with 4 port hub
    • 4 lane Gen 2.0 PCI-Express slots (Juno r1 only)
  • Debug
    • ARM JTAG : 20-way DIL box header
    • ARM 32/16 bit parallel trace

Title     Description 
Juno Getting Started Guide Introduction to the Juno platform
Juno r0 ARM Development Platform Technical Reference manual   Juno r0 Technical reference manual for the development board, detailing board peripherals, memory map interrupts etc.
Juno r0 SoC Technical Reference manual Juno r0 Technical reference manual for the SoC
Juno r0 ARM Development Platform datasheet Juno r0 Datasheet summarising the hardware and software features of this platform.
Juno r0 ARM Development Platform Soc Technical Overview Juno r0 Technical overview of the  platform covering both software and hardware features.
Juno Software Developers Errata Notice List of errata for software developers.
Juno r1 ARM Development Platform Technical Reference manual Juno r1 Technical reference manual for the development board.
Juno r1 SoC Technical Reference manual Juno r1 Technical reference manual for the SoC
Juno r1 ARM Development Platform datasheet Juno r1 Datasheet summarising the hardware and software features of this platform.
Juno r1 errata document Juno r1 errata document
 

 

 

The Juno ARM Development Platform can be expanded by adding a Versatile Express LogicTile 20MG FPGA development board. This allows the addition of user logic to the system. The FPGA board connects to the platform using master & slave Thin Links as a method off chip communication.

An application note AN415 on how to to connect an ARM LogicTile Express 20MG to the Juno Development Platform is available to download here  

The Juno r1 variant can also be expanded using the 4 Gen 2.0 PCI-Express slots.

 


 

 

  • Development Platform
    • The Juno hardware delivers to software developers an open, vendor neutral ARMv8 development platform with
      • Cortex® A57 and A53 MPCore™ for ARMv8 (big.LITTLE Juno r0 only)
      • Mali™-T624 for 3D Graphics Acceleration and GP-GPU compute
      • 4 lane Gen 2.0 PCI-Express expansion (Juno r1 only)
      • A SoC architecture aligned with Level 1 (Server) Base System Architecture

 

With out-of-the-box support for the Juno ARM Development Platform, ARM DS-5 Ultimate Edition is the complete tool suite for ARM, including ARMv8. Enabling code generation, debug, trace and optimization of software from bare-metal to userspace, DS-5 has been developed alongside the ARMv8 architecture to help take full advantage of ARM’s highest performance processors.

It offers OS-aware debug for Linux and Android, along with a range of RTOSs, keeping track of threads and processes across multicluster and big.LITTLE configurations is intuitive. System optimization is made easier with excellent support for advanced CoreSight debug and trace, whilst Streamline performance analyzer helps identify bottlenecks in CPU and Mali GPU, which can be tracked down to individual functions or lines of source code.   


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