The CoreLink™ Static Memory Controllers (SMC) provide efficient interfaces to a wide range of types of non-volatile memory, leveraging the features of AMBA AXI to schedule requests to the memory in the most optimal fashion. They are designed for compatibility with the ARM portfolio of Why choose a CoreLink Static Memory Controller?
Most systems with ARM processors will have off-chip static (non-volatile) memories. These will contain information such as object code and data files. System performance depends on being able to read and write this data efficiently and accurately.
CoreLink Static Memory Controllers are available for AMBA AXI (SMC-35X) and AMBA AHB (PL24X). These controllers are optimized for the bus protocol and have been developed to complement the CoreLink Network Interconnect and Dynamic Memory Controllers along with ARM CPU and media processors.
Verification and Benchmarking
Understanding the performance and functionality of the memory controller in a system context is critical to the specification and development of the controller. The system level verification and benchmarking that we perform ensures that we deliver products that have been fully qualified alongside the cores and on-chip interconnect. These results then drive the specifications of both current and future memory controllers. They ensure our Partners have the efficient, low-risk, easy to integrate solutions that enable development to proceed smoothly - meeting performance goals and delivering time to market.
And for the future?
ARM is committed to ensuring the ARM ecosystem has the memory controller solutions our Partners require. We participate in the industry standards bodies defining new memory interfaces to ensure that they meet the needs of our Partners. Collaboration with ARM teams developing new cores and new interconnects ensures that memory interface support for new products is available to our partners when they need it.
