The ARM® CoreLink™ DMC-520 Dynamic Memory Controller is specifically designed to provide an optimal solution for infrastructure applications including servers, enterprise, HPC and networking.
Optimized and efficient access to the DRAM is critical to the performance of any Infrastructure SoC. As the number of processing elements on a chip increases so does the demand for data. With DRAM technology transitioning to DDR4, not only does the frequency of DRAM operation increase to 3200 Mbps, but also the complexity of making best use of the DRAM bandwidth to deliver high quality of service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while trying to make optimum use of DRAM is the challenge faced by a Dynamic Memory Controller (DMC).
Rapid access to memory for enterprise SoCs
The ARM CoreLink DMC-520 Dynamic Memory Controller is specifically designed to provide an optimal solution for infrastructure applications including servers, enterprise, HPC and networking. In a wide range of test scenarios, CoreLink DMC-520 achieves greater than 90% utilization of theoretical maximum DRAM bandwidth.
CoreLink DMC-520 has been designed to meet the needs of an Infrastructure system based around a Cache Coherent Network product from ARM. CoreLink DMC-520 is a key part of ARM's End-to-End Quality of Service (QoS) scheme that includes features distributed across both Interconnect and Memory Controllers. These features ensure that bandwidth and latency contracts for memory access from various system elements are successfully fulfilled without penalizing any specific element.
The CoreLink DMC-520 provides a high bandwidth interface to shared off-chip memory, such as DDR4, DDR3 and DDR3L DRAM along with full DIMM support. Enterprise class RAS (Reliability, Availability and Serviceability) features such as SECDED and enhanced symbol-based ECC for x72/x40 DRAM, and TrustZone security are integral components of this memory controller. CoreLink DMC-520 uses the DFI 3.1 interface to enable integration with a DFI-compliant DDR PHY and has proven interoperability with various customer and 3rd party DDR PHYs.