CoreLink CCN-504 Introduction
CoreLink CCN-504 is the first in a family of Cache Coherent Network products. It enables a fully-coherent, high-performance many-core solution that supports up to 16 cores on the same silicon die. The CoreLink CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems, such as those required for the networking and high-performance computation markets, by enabling each processor in the system to access the other processor caches. This reduces the need to access off-chip memory, saving time and energy, which is a key enabler in systems based on ARM big.LITTLE™ processing, a new paradigm that can deliver both high-performance, required for content creation and consumption, while also delivering extreme power efficiency for extended battery life.
Optimised for ARM Cortex Processors
The CoreLink CCN-504 supports the high performance Cortex-A15 processor and the latest Cortex-A53 and Cortex-A57 processors, and is the first interconnect product to support AMBA® 5 CHI. This new coherent hub interface has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors especially for the enterprise networking and server applications this product aims to address. The CoreLink CCN-504 benefits from ARM experience in hardware-based coherency, that enables improved energy-efficiency and lower latency than software managed coherency.
Integrated Low Latency Level 3 Cache
The CoreLink CCN-504 Cache Coherent Network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.
High Performance DDR3 and DDR4 Memory Interfaces
The CoreLink CCN-504 is optimised to work with the CoreLink DMC-520 Dynamic Memory Controller. The CoreLink DMC-520 provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. Enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and End to End QoS are integral components of this new memory controller. CoreLink DMC-520 is part of an integrated ARM DDR4/3 interface solution incorporating Artisan® DDR4/3 Phy IP planned for introduction in 2013.
CoreLink CCN Cache Coherent Network Series
CoreLink CCN-504 Cache Coherent Network is the first in a series of products designed for high performance, power efficient server and network infrastructure products. ARM will be announcing further products to allow our partners to optimise the interconnect for their system requirements.
ARM leadership in scalable, power-efficient multi-core and ‘many-core’ technology will address the demand for energy-efficient SoC solutions for use in servers and network infrastructure. As these markets are increasingly power- and cost-constrained, the effectiveness of these ‘many-core’ processor clusters rely on the whole system being optimized.