CoreLink NIC Family

The ARM® CoreLink™ Network Interconnect offers highly configurable topology with Network on Chip (NoC)-like properties that enable you to build high performance, optimized, AMBA®-compliant SoC connectivity.

Low Power AMBA 4 AXI Interconnect

Rapid design

CoreLink NIC-450 offers a fast, automated, verified subsystem creation that is correct-by-construction when used with the Socrates™ CoreLink Creator. It allows monitoring of true master-slave-master performance through the interconnect system and SoC designers can be assured the use of correct algorithms to ensure a deadlock-free design.

Silicon proven

CoreLink NIC can be tailored to suit your system requirements, having been successfully used in billions of devices

Low power, low latency

CoreLink NIC are the lowest power AXI interconnects with QoS enhancements that ensure low latency communication across the chip

CoreLink NIC-450 Network Interconnect for non-coherent data
ARM Developer Resources

Looking for
Technical Information?

Developer Resources

Configurable System Interconnect

The ARM CoreLink NIC-450 Network Interconnect is a system interconnect that offers a tool-driven flow for rapid, optimized configuration. It ensures deadlock-free operation and partitioning across multiple power/voltage domains to build the lowest latency, highest area applications for AMBA 4, AMBA 3 and AMBA 2.

CoreLink NIC-450 delivers key technologies that create vast on-chip networks, such as:

  • Ability to distribute switching and routing functions between many and complex IP blocks
  • Predictability of physical implementation
  • Communication control for system performance optimization
  • Communication visibility for software optimization
  • Reliable integration of complex system containing third party IP core

Use Cases

Default Headline

Premium Mobile or Tablet big.LITTLE

  • Quad-core big with quad-core LITTLE processor
  • Mali GPU
Default Headline

Mid-range Mobile big.LITTLE

  • Dual-core big and quad-core LITTLE processor
  • Mali GPU
Default Headline

Entry Level Mobile

  • Octa-core LITTLE solutions
  • Mali GPU
Default Headline

Smart TVs and Set-top boxes

  • Dual quad-core big processor and dual or quad-core LITTLE
  • Mali GPU
Default Headline

Wearable devices

  • Single cluster design requiring low power and low latency
Default Headline

Rich embedded applications

  • Single board computer

White Papers

Introduction to AMBA 4 ACE and big.LITTLE Processing Technology

Introduction to AMBA 4 ACE and big.LITTLE Processing Technology

This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, distributed virtual memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency.


Quality of Service in ARM Systems: An Overview

Quality of Service in ARM Systems: An Overview

Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems.


QoS for High-Performance and Power-Efficient HD Multimedia

QoS for High-Performance and Power-Efficient HD Multimedia

Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.


Introduction to QoS Virtual Networks (QVN)

Introduction to QoS Virtual Networks (QVN)

This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.



We use cookies to give you the best experience on our website. By continuing to use our site you consent to our cookies.

Change Settings

Find out more about the cookies we set