CoreLink CCN Family

Growth in mobile computing and the Internet of Things is connecting more devices and aggregating more data across the network, and that demands an increasingly flexible and efficient computing infrastructure.

The ARM® CoreLink™ CCN Cache Coherent Network family offer the solution with scalable, high performance cache coherency and shared system cache for ARM Cortex® processors, memory and IO such as accelerators and network interfaces. This family of interconnects offers an optimized solution for a wide range of networking infrastructure and server applications.

Infrastructure interconnect from ARM

Optimized for ARM Cortex Processors

The CoreLink CCN family support the latest ARM 64-bit processors and are native AMBA® 5 CHI (Coherent Hub Interface) protocol. This enables high frequency, non-blocking data transfers between multiple fully coherent processors.

Integrated Low Latency Level 3 System Cache

The CoreLink CCN includes an optional integrated configurable system cache and snoop filter functions. The system cache extends on-chip caching for demanding workloads and offers low latency for allocation and sharing of data between processors, high-speed IO interfaces and accelerators.

High Performance DDR3 and DDR4 Memory Interfaces

The CoreLink CCN family is optimised to work with the CoreLink DMC-520 Dynamic Memory Controller providing a high-bandwidth interface for off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. CoreLink DMC-520 offers enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and End to End QoS.

Quality of Service

The CoreLink CCN family with CoreLink DMC-520 use ARM intelligence to shift bandwidth and latency when required, offering end-to-end regulation for CPUs and IO peripherals.

Energy efficient networking

Power usage is a major concern for servers as it represents a significant cost in the datacenter. ARM Cache Coherent Networks are designed for performance at power benchmarks, delivering efficiency that dramatically reduces the total cost of ownership of servers

Proven technology

CoreLink CCN technology is a silicon-proven, mature technology and has already been licensed by 10 partners and has been shipped in production designs. It is part of a complete infrastructure solution including Cortex processors, CoreLink DMC-520, MMU-500 and GIC-500.

CoreLink CCN Cache Coherent Network in an enterprise system
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A scalable solution

The CoreLink CCN family offer a range of solutions, each including configuration options, to allow silicon partners to customize the optimal configuration of interconnect, processor clusters, caches, memory and IO interfaces. By choosing the right interconnect for the right job, partners can get the exact performance and system characteristics while minimizing area and power.

Feature CCN-502 CCN-504 CCN-508 CCN-512
Key benefits Smallest CCN interconnect, Optional L3 Highest performance 4 cluster interconnect 8 cluster interconnect, high IO bandwidth 12 cluster interconnect, highest compute performance
Processor clusters 1-4 1-4 1-8 1-12
Use cases WiFi access point, DSL modem, Set top box, Home gateway Edge Router, Small cell base station, SDN SDN, Edge server, Macro cell base station, Base station controller Cloud RAN equipment, Core networking equipment, NFV

The CoreLink Cache Coherent Network family provides a scalable solution for any type of infrastructure SoC.

Default Headline

"While these software approaches are highly beneficial, it is just as important to have hardware that is optimized for these new models. The QorIQ LS series of chips use the ARM CoreLink CCN-504 Cache Coherent Network as an interconnect solution to maintain full coherency across processor hubs resulting in optimum performance. Its L3 cache reduces latency which in turn reduces the power requirements of the SoC, an important consideration in network applications." NXP QorIQ 2045 or 2085

White Papers

Introduction to AMBA 4 ACE and big.LITTLE Processing Technology

Introduction to AMBA 4 ACE and big.LITTLE Processing Technology

This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, distributed virtual memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency.


Quality of Service in ARM Systems: An Overview

Quality of Service in ARM Systems: An Overview

Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems.


QoS for High-Performance and Power-Efficient HD Multimedia

QoS for High-Performance and Power-Efficient HD Multimedia

Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.


Introduction to QoS Virtual Networks (QVN)

Introduction to QoS Virtual Networks (QVN)

This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.



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