CoreLink CCN-508

CoreLink CCN-508 Image (View Larger CoreLink CCN-508 Image)
The ARM® CoreLink™ CCN-508 Cache Coherent Network extends energy efficiency to enterprise solutions scaling up to 32 processor cores. This gives system architects the flexibility to create optimal solutions for enterprise applications including storage, servers and network infrastructure.

Consumers are generating exponential growth in data handling requirements which is driving significant infrastructure changes for networking and servers. The changes demand more energy efficient solutions and ARM based SoC solutions can uniquely solve these requirements with efficient processors and CoreLink System IP.

CoreLink CCN-508 can deliver up to 1.6 terabits of sustained usable system bandwidth per second with a peak bandwidth of 2 terabits per second at processor speeds. It will enable designers to provide high-performance, cache coherent interconnect for ‘many-core’ enterprise solutions built using the latest Cortex-A57 and Cortex-A53 processors which both integrate 64-bit support.

CoreLink CCN-508 is the second interconnect to support the AMBA® 5 CHI standard, designed to support high frequency, non-blocking data transfers between multiple fully coherent processors.



ARM CoreLink CCN-508 is the second in a family of Cache Coherent Network products.  It enables a fully-coherent, high-performance many-core solution that supports up to 32 cores on the same silicon die, enabling true System on Chip solutions. The CoreLink CCN-508 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems, such as those required for the networking and high-performance computation markets, by enabling each processor in the system to access the other processor caches. This technology reduces the need to access off-chip memory, saving time and energy, which is a key metric for enterprise customers. CoreLink CCN-508 also enables systems based on ARM big.LITTLE™ processing, which delivers both high-performance, required for content creation and consumption, and extreme power efficiency for extended battery life.  

Optimized for ARM Cortex Processors

The CoreLink CCN-508 supports the high performance and efficient cores including the Cortex-A57 and Cortex-A53 processors, and is the second interconnect product to support the AMBA 5 CHI standard. This new CHI (Coherent Hub Interface) has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors. It is especially suited for enterprise networking and server applications.

Integrated Low Latency Level 3 Cache

The CoreLink CCN-508 Cache Coherent Network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 32MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.

High Performance DDR3 and DDR4 Memory Interfaces

The CoreLink CCN-508 is optimized to work with the CoreLink DMC-520 Dynamic Memory Controller. The CoreLink DMC-520 provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. Enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and End-to-End QoS (Quality of Service) are integral components of this new memory controller.

CoreLink CCN Cache Coherent Network Series

CoreLink CCN-508 Cache Coherent Network is the second in a series of products designed for high performance, power efficient server and network infrastructure products.  ARM leadership in scalable, power-efficient multi-core and ‘many-core’ technology already addresses the demand for energy-efficient SoC solutions for use in servers and network infrastructure. The Cache Coherent Network series of products enable our partners to expand their product lines with highly competitive solutions that bring outstanding efficiency to these markets.


Bandwidth and Latency

CoreLink CCN-508 Cache Coherent Network can deliver up to 1.6 terabits per second of usable system bandwidth. It will enable designers to provide high-performance, hardware managed cache coherency between processor clusters and IO interfaces and accelerators. Bandwidth to the quad channel DDR4 memory approaches 75GB/s.


CoreLink CCN-508 is designed to work closely with the latest ARM Cortex applications processors and can be implemented at clock speeds that match the Cortex-A53 or Cortex-A57 processor. Interfaces to memory and processors can be configured for asynchronous interfaces to allow power management including dynamic voltage and frequency scaling

CoreLink CCN-508 Specification

Usable system bandwidth: < 1.6 Terabit/second
Frequency: Up to CPU frequency
CPUs supported Cortex-A57, Cortex-A53 and future A50 series processors
Bus width         128 bit inbterfaces 
Scalability Up to 32 cores (8 coherent clusters)
Level 3 cache Integrated, configurable 1-32MB
Snoop filter Integrated to minimize snoop broadcast
Low power support Extensive clock gating, leakage mitigation hooks
Granular DVFS and CPU shutdown support
Partial or full level-3 cache shutdown
Retention modes
IO             Up to 24 ports
AMBA 4 AXI4/ACE-Lite interfaces supported
DDR 4 channels supported with CoreLink  DMC-520
RAS ECC on RAMs and parity on transport
QoS Integrated QoS regulation and priority management
Security ARM TrustZone® aware

ARM Cortex Processors

CoreLink CCN-508 offers hardware coherent ‘many-core’ enterprise solutions built using the 64-bit capable ARM Processors.

CoreLink System IP

CoreLink CCN-508 is one part of a system solution available from ARM including:

Interface Specifications

CoreLink CCN-508 supports AMBA 5 CHI and AMBA 4 ACE, ACE-Lite and AXI4 interfaces. More information available from the AMBA Open Specifications page.    

Graphics Processors

ARM Mali™ Graphics Processors including Mali-T600 series of GPUs can be connected to the ACE-Lite interfaces of CoreLink CCN-508 to provide hardware IO Coherent graphics acceleration.

Physical IP

ARM Artisan® provide standard cell library and compiled RAM for implementation of CoreLink CCN-508.



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