The ARM® CoreLink™ CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of ARM systems in a range of applications.
Mobile systems designers need to support high resolution screens, complex applications and console quality graphics. The Cache Coherent Interconnect is a critical part of the mobile SoC, it provides full cache coherency between big.LITTLE™ processor clusters and provides IO coherency for other agents such as Mali™ GPU, network interfaces or accelerators.
CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet their performance goals with the smallest possible area and power. CoreLink CCI-500 is a 4th generation coherent interconnect from ARM, building on the broad licensing and wide design wins of the previous generation CoreLink CCI-400.
Introduction to the ARM CoreLink CCI-500
ARM CoreLink System IP plays a key role in enabling partners deliver optimized ARM-based SoCs. The CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of ARM mobile systems.
CoreLink CCI-500 Infographic
Learn how CoreLink CCI-500 is central to ARM-based systems; supporting high resolution screens complex applications and console quality graphics
Optimized Mobile Interconnect
CoreLink CCI-500 is a high performance interconnect solution, delivering improvements on key benchmarks associated with system performance. Benchmarking vs the previous generation shows:
- Up to 2x peak system bandwidth
- +30% processor memory performance
- 12% memory system power savings
Seamless 4K Content
Premium mobile devices are driving higher resolution screens such as 4K Ultra-HD content, external displays, and console quality gaming content. CoreLink CCI-500 offers up to 34GB/s peak system bandwidth to enable seamless 4K content to mobile devices. This represents 2x peak system bandwidth compared to CoreLink CCI-400
+30% Processor Performance
Benchmarking tests show CoreLink CCI-500 offers a 30% increase in processor memory performance. This enables a more responsive user interface for complex tasks like productivity applications such as AutoCAD, video editing and increased multi-tasking.
Central to ARM systems
CoreLink CCI-500 is an important part of the complete system. It has been designed and tested with ARM Cortex processors, Mali Graphics, CoreLink System IP and CoreSight debug and trace to provide system performance that is highly optimised.
CoreLink CCI-500 is part of a complete suite of system IP from ARM including CoreLink NIC-400 network interconnect for low power, low latency, end to end connectivity to the rest of the SoC, CoreLink MMU-500 system MMU for virtualization of IO and CoreLink GIC-500 for management of interrupts across multiple processor clusters.
Premium Mobile or Tablet big.LITTLE
- Quad-core big with quad-core LITTLE processor
- Mali GPU
Mid-range Mobile big.LITTLE
- Dual-core big and quad-core LITTLE processor
- Mali GPU
Entry Level Mobile
- Octa-core LITTLE solutions
- Mali GPU
Smart TVs and Set-top boxes
- Dual quad-core big processor and dual or quad-core LITTLE
- Mali GPU
Industrial and Automotive Infotainment
- Quad-core big processor with quad-core LITTLE
- Mali GPU
Introduction to AMBA 4 ACE and big.LITTLE Processing Technology
This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, distributed virtual memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency.
Quality of Service in ARM Systems: An Overview
Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems.
QoS for High-Performance and Power-Efficient HD Multimedia
Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.
Introduction to QoS Virtual Networks (QVN)
This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.