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CoreLink CCI-400 Cache Coherent Interconnect

Modern SoCs combine multiple processors which allow for more optimized performance, and the interconnect needs to deliver shared data to make this possible. The ARM® CoreLink™ CCI-400 provides coherency across the system, which increases performance and improves power efficiency. CoreLink CCI-400 is a high performance, power efficient interconnect designed to interface between processors and the memory controller.

Coherency increases performance optimization

Example implementations of hardware coherency are as follows:

big.LITTLE processing: Hardware coherency is fundamental to big.LITTLE™ processing as it allows the big and LITTLE processor clusters to see the same view of memory and run the same operating system.

GPU Compute: Hardware coherency reduces the cost of sharing data between CPU and GPU, and allows tighter coupling. This means that the GPU can read any shared data directly from the CPU caches, and writes to shared memory will automatically invalidate relevant lines in CPU caches.

Networking & server: Enterprise applications such as networking and server have high performance serial interfaces such as PCI Express, Serial ATA and Ethernet. In most applications all of this data will be marked as shared as there will be many cases where the CPU needs to access data from these serial interfaces.

Silicon proven

CoreLink CCI-400 has been licensed over 40 times. It has been involved in multiple successful tapeouts and has been shipped in hundreds of millions of devices.

 
CoreLink CCI-400 in a mobile system
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CoreLink CCI-400 is a configurable design that can be used in different applications. Its low power, high performance is well suited to mobile, wearable, embedded and automotive designs.

 

Use Cases

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Mobile

  • Octa-core LITTLE solutions
  • Mali GPU
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Wearable

  • Dual-core big and dual-core LITTLE
  • Mali GPU
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Embedded

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Automotive

White Papers

Introduction to AMBA 4 ACE and big.LITTLE Processing Technology

Introduction to AMBA 4 ACE and big.LITTLE Processing Technology

This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, distributed virtual memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency.

 

Quality of Service in ARM Systems: An Overview

Quality of Service in ARM Systems: An Overview

Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems.

 

QoS for High-Performance and Power-Efficient HD Multimedia

QoS for High-Performance and Power-Efficient HD Multimedia

Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

 

Introduction to QoS Virtual Networks (QVN)

Introduction to QoS Virtual Networks (QVN)

This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.

 



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