CoreLink CCI-400 Cache Coherent Interconnect for AMBA 4 ACE

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Massive growth in system integration places on-chip communication at the center of system performance. The CoreLink™ CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs, such as the Cortex™-A15 and Cortex™-A7 for big.LITTLE processing; and I/O coherency for devices such at the Mali™-T604 GPU, and I/O masters like modem and USB. To date ARM has licensed the CCI-400 product to over 10 licensees including LSI, HiSilicon, STEricsson, Fujitsu and LG.

The CCI-400 implements the AMBA® 4 ACE™ and ACE-Lite™ protocols (PDF Download - Registration / Login Required)

Why CoreLink CCI-400?

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CoreLink CCI-400 Cache Coherent Interconnect

The CCI-400 is a high performance, power efficient interconnect designed to interface between processors and the dynamic memory controller, such as the CoreLink DMC-400. It is the first product to implement AMBA® 4 ACE™, which brings system coherency, virtual memory management signalling and barriers.

Coherency enables scaling. The latest SoC designs have more processors and more shared data due to an increase in processor cores and accelerator engines including multimedia, and GPU. These additional processors increase system performance and improve power efficiency but all the data shared between these processors needs to be managed.

To manage shared data there are three techniques:

Disable caching: all shared memory is written externally to DDR. This is the simplest solution but expensive in external accesses and latency.
Software managed coherency: any data stored in processor caches must be cleaned and flushed to external memory before passing to accelerators and other hardware. This requires the CPU software to actively manage cached data.
Hardware managed coherency: the system interconnect ensures all shared data is coherent in the system, reduces external memory accesses and removes the need for software to manage caches. This offers improved performance and power efficiency.

The CCI-400 enables hardware managed coherency between two AMBA 4 ACE processor clusters such as Cortex-A15 and Cortex-A7, allowing scaling of system performance up to 8x cores in total, and supporting big.LITTLE processing.

I/O coherency, or one way coherency, is also supported for up to three accelerator engines implementing the AMBA 4 ACE-Lite protocol.

The CCI-400 benefits are not limited to coherency, this product also supports the virtualization extensions including a low latency connection to a system MMU, such as CoreLink MMU-400, to allow virtualization of hardware devices. This could be used to take advantage of multiple OS’s running on the same hardware, or simply a more efficient way to share limited physical memory.

The CCI-400 also supports the propogation of barriers to enforce the ordering of transactions, while allowing the processors to generate many outstanding transactions, so minimizing CPU stalls awaiting the completion of preceding transactions.

High bandwidth, low latency CCI-400

The CoreLink CCI-400 cache coherent interconnect is targeted to run at up to half the frequency of the Cortex-A15 processor to allow high performance, low latency connection to main memory.

All interfaces support 128-bit wide data allowing for systems scaling to 10’s Gbyte/s data bandwidths to support high definition multimedia requiremens and the latest high performance networking interfaces.

The CCI-400 is designed to minimize latency to ensure the maximum performance of latency-sensitive processors.

For low power designs the interconnect can be configured for lower bandwidth if required, and reduced latency can be offered for lower frequency targets.

For further details please contact ARM.

ACE interfaces	2x ACE interfaces for processor clusters, such as quad Cortex™-A15 or Cortex™-A7 MPCore™ Processors.
ACE-Lite interfaces	3x ACE-Lite slave interfaces for connecting hardware accelerators, media processors, such as Mali™-T604, Mali™-T658, and extending to further masters via the CoreLink NIC-400.
System and DMC interfaces	3x ACE-Lite master interfaces for connecting up to 2x dynamic memory controllers such as CoreLink DMC-400 and 1x system connection port via the CoreLink NIC-400
128-bit data width	All read and write data channels are of fixed, 128-bit width
AXI support	Backwards compatibility for AXI4 devices
Memory map	Configurable across 40-bit address space, includes support for interleaving between 2 memory controllers.
Coherency	Full cache coherency for ACE masters, I/O coherency for ACE-Lite masters
Barriers	Handled within interconnect or propagated to downstream ACE-Lite devices
QoS	Integrated QoS mechanisms for traffic management, designed to work optimally with compatible IP including NIC-400 and DMC-400 for end-to-end Quality of Service.
Distributed Virtual Memory (DVM)	Supports broadcast of DVM signalling to attached processors and system MMU, such as CoreLink MMU-400.
Configurable	Parameter defined interconnect, such as the number of transactions and pipeline stages are configurable to allow the design to meet a range of performance and area targets.
Low Power	Integrated clock gating allows full clock tree to be turned off in idle and near idle conditions.

Further information is available in the Technical Reference Manual available on request from your ARM Sales contact.

Interconnect	Related Product	Benefit
CoreLink CCI-400	Cortex-A15	Full cache coherency between clusters via ACE interface
	Mali-T604	I/O coherency with ACE masters via the ACE-Lite port
	CoreLink DMC-400	End-to-end Quality of Service
	CoreLink NIC-400	End-to-end Quality of Service
	CoreLink MMU-400	system wide memory management via DVM signalling