CoreLink CCI-400 Cache Coherent Interconnect
The CoreLink CCI-400 is a high performance, power efficient interconnect designed to interface between processors and the dynamic memory controller, such as the CoreLink DMC-400. It is the first product to implement AMBA® 4 ACE™, which brings system wide hardware coherency and virtual memory management.
What is hardware coherency?
Coherency enables scaling. The latest SoC designs have shared data due to an increase in processor cores and accelerator engines including multimedia, and GPU. These additional processors increase system performance and improve power efficiency, however this shared data needs to be managed to ensure everyone sees the same view.
To manage shared data there are three techniques:
- Disable caching: all shared memory is written externally to DDR. This is the simplest solution but expensive in high power external accesses and latency.
- Software managed coherency: any data stored in processor caches must be cleaned and flushed to external memory before passing to accelerators and other hardware. This requires the CPU software to actively manage cached data, and requires CPU resources.
- Hardware managed coherency: the system interconnect ensures all shared data is coherent in the system, reduces external memory accesses and removes the need for software to manage caches. This can offer improved performance and power efficiency as the CPU can do useful work or enter a lower power state.
Processor support and big.LITTLE
The CCI-400 enables hardware managed coherency between two AMBA 4 ACE processor clusters such as the ARM Cortex-A15, Cortex-A7, Cortex-A57 and Cortex-A53, allowing scaling of system performance up to 8x cores in total. Hardware coherency with CoreLink CCI-400 is a fundamental part of ARM big.LITTLE processing. This offers the ability for processos and applications to dyanmically move between the high performance 'big' and the high efficiency 'LITTLE' processor cluster.
Hardware I/O Coherency and System MMU
I/O coherency, or one-way coherency support is provided for up to three accelerator engines implementing the AMBA 4 ACE-Lite™ protocol. This could include Graphics processors such as ARM Mali™-T600 series, or interface controllers such as USB, Ethernet, and WiFi.
The CoreLink CCI-400 benefits are not limited to coherency, this product also supports the virtualization extensions including a low latency connection to a system MMU, such as CoreLink MMU-400 or MMU-500, to allow virtualization of hardware devices. This can take advantage of multiple OS’s running on the same hardware, or simply a more efficient way to share limited physical memory.
