CoreLink Network Interconnect for AMBA AXI

Low power is also important to ARM, and the CoreLink Network Interconnect is no exception. The RTL is optimized to make extensive use of automated clock gate insertion by synthesis tools. Implementation trials have shown that as many as 95% of the flops are clock gated when idle.

Small interconnect switches with few ports are faster than large switches with many ports, therefore the latest CoreLink Network Interconnect allows for the generation and stitching of a network of small switches. This network of switches strategy improves the overall performance for a system. In addition, each switch can operate on its own clock domain. Defined to be asynchronous, they allow easier timing closure across a large silicon die.

Network of interconnects (NIC-400, NIC-301)

An instance of the product is a network of interconnects. Creating complex systems is easy and configuration options checked for consistency

• Topology design to match floor plan & dataflow requirements
• Interface-and-switch architecture optimizes logic between interconnects for lower gate count

Virtual networks to prevent blocking

An option (QVN-400) uses priority controlled allocation of buffer space in the NIC-400 interconnect and DMC-400 memory controller to prevent cross-line and head-of-line blocking throughout the entire path form processors to memory.

Thin Links

An option (TLX-400) available for the NIC-400 to reduce routing between AXI switches

Long Bursts in AMBA 4 AXI4

The new NIC-400 adds support for long bursts to improve the efficiency of media streaming

Lower power with hierarchical clock gating

Added with the NIC-400 to reduce idle power by over 90%.

Optimized translation latency

Only one latency penalty for any combination of clock, data width and protocol translations

Single cycle arbitration

Arbitration has single-cycle throughput and single-cycle switching so that there are no pipeline bubbles

Global dynamic QoS

QoS information travels dynamically with the transaction through the network of interconnects, for distributed arbitration in a network structure

Enhanced buffering to reduce stall

Buffering can be configured in each channel at crossing points to accept transactions so that stall is not induced in critical communication paths

Multiple outstanding transactions through downsizer

When reducing data width, a configurable number of outstanding transactions can be processed simultaneously

Up-sizer packs data into wide bus

Narrow data efficiently packed onto the wide data path

Internally programmable

Programming of the network is address mapped inside of the network so that no external loop-back connections are necessary

System-level address map

System-level address map described independently of network design.  Masters can have independent address maps

Extended timing closure options

timing closure options per AXI channel & per direction (forwards, reverse)

• Either side of network interface
• At translation boundary
• Between switches
• Post-arbitration
• Intra-arbitration

256-bit maximum data width

256-bit maximum data width, with translations to- and from- 32-bit data

Multi-region slave support

Decoding of sparse slaves is precise, and errors are reported from the interconnect

Write-data release control

In network interfaces, the release of write data can be programmed to remove bubbles from the data path when data is not received in consecutive cycles