The ARM CoreLink™ NIC-400 Network Interconnect provides a fully configurable, hierarchical, low latency, low power connectivity for AMBA® 4 AXI4™, AMBA 3 AXI3™, AHB™-Lite and APB™ components. The NIC-400 adds new features over the NIC-301 such as advanced power management with heirarchical clock gating and options for Thin Links to reduce routing congestion and QoS Virtual Networks to prevent blocking.
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- Quality of Service (QoS)
- Why CoreLink NIC-400?
- Related Products
Advanced Quality of Service (QoS-301, QoS-400) is an option for the CoreLink™ Network Interconnect (NIC-400) products, and gives the SoC architect the essential tools to efficiently share the finite bandwidth of critical interfaces like DDR memory.
On-chip data flows have a number of requirements that need to be met concurrently through the interconnect & memory controller, for example
- Maximum latency for display controller to prevent dropped frames
- Bandwidth critical DMA
- Latency sensitive CPU
As part of an appropriate system design Advanced Quality of Service (QoS-301, QoS-400) can guarantee worst-case latency and bandwidth, and minimize average latency. This maximizes Cortex™ processor application performance and guarantees user experience for Mali™ GPU-based graphics and video in complex multimedia systems.
Features of the CoreLink Advanced Quality of Service
QoS manages data traffic at entry to the network interconnect using targeted hardware resource for critical components. QoS, in combination with the CoreLink Dynamic Memory Controllers (DMC-400, DMC-34x):
- Minimizes average latency for best-effort masters,
- Whilst guaranteeing bandwidth & latency for real-time traffic.
QoS dynamically adjusts a master's priority to meet its target transaction latency. Masters operate at the lowest priority they need, freeing system resources for use by others. Traffic shaping manages the system queues and guarantees the memory controller queue does not block other paths in the interconnect.
QoS is fully integrated with AMBA Designer, allowing the SoC designer to configure the QoS hardware alongside the CoreLink Network Interconnect (NIC-400, NIC-301).
QoS Virtual Networks prevent blocking
QoS Virtual Networks (QVN-400) use a priority driven allocation of buffer space in both the interconnect (NIC-400) and the memory controller (DMC-400) to provide virtual channels over the same set of resources to prevent cross-stream and head-of-line blocking. This ensures that there is always a clear path for higher priority traffic types such as timeout critical transfers and latency sensitive CPU loads, while at the same time making the maximum amount of bandwidth available to latency-tolerant masters such as media processors.
Optimize for efficiency and guarantee performance
Traditional system design has required the architect to over-engineer the implementation to guarantee performance. Using Advanced Quality of Service allows the architect to better optimize the design and using hardware to control the traffic flows in the system.
Whitepapers on QoS:
Quality of Service in ARM Systems : An Overview (Connected Community)
Introduction to the QVN Protocol (Connected Community)
- QoS for High-Performance and Power-Efficient HD Multimedia (PDF 4MB)
- Traffic Management for Optimizing Media-Intensive SoCs (PDF 1MB)