CoreSight STM-500 System Trace Macrocell

The ARM® CoreSight™ STM-500 System Trace Macrocell gives real-time SoC level visibility at affordable cost up to end product.

The System Trace Macrocell enables real-time instrumentation of software without altering system behavior and real-time analysis of the platform behavior and performance. For software, system and hardware engineers, visibility of the complete system is now critical to deliver high performance, power optimized systems in shorter development cycles.

The ARM CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers, in particular application and kernel developers, enabling rich, optimized and low power software on ARM processor-powered devices across the whole supply chain.


CoreSight STM for debug visibility

The STM delivers:

  • Low-latency, high-bandwidth, non-intrusive and time stamped software instrumentation of the kernel and user space, enabling software developers to gain more visibility on how their software execute without altering the behaviour of the system
  • An industry standard for instrumentation trace enabling any software running on any master to use this resource
  • A scalable solution enabling multi-processors and processes to access STM without being aware of others; STM supports 65,536 channels enabling significant scalability

Low latency, high performance software instrumentation

The STM enables low latency and high bandwidth printf style debug capability that gives developers more visibility into their software without altering the system behaviour, making it easier to develop and optimize software on ARM processor-based systems.

System performance tuning and debug

To system developers, the STM provides timing-accurate on-chip visibility of the software and hardware interaction, enabling ARM silicon partners and OEMs to optimize even further their SoCs and bring their platforms to market faster.

An industry standard

The CoreSight System Trace Macrocell offers an industry standard across all markets for system visibility. All major tool vendors will support ARM system trace macrocells.

STM complements the industry standard Embedded Trace Macrocell® (ETM®) and is compliant with MIPI® System Trace specification.

ARM System Trace for Cortex-A and Cortex-R Processor-based SoC

The CoreSight System Trace Macrocell is architected to provide low latency and high bandwidth real-time system instrumentation required for real-time and application based platforms.

The ARM STM supersedes the Instrumentation Trace Macrocell (ITM) for these applications; for Cortex®-M series processor-based devices, ITM remains the preferred solution.

STM Key performance characteristics

  • Designed to operate at system frequency for Cortex-A and Cortex-R processor-based SoC (e.g. at least 400MHz on 65LP)
  • 32-bit data trace path (32-bit AXI interface, 32-bit ATB interface) for high bandwidth and low latency system instrumentation
  • Fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Compatible with the latest MIPI® System Trace protocol

CoreSight debug and trace for real time visibility
ARM Developer Resources

Looking for
Technical Information?

Developer Resources

Customer Successes


"ARM CoreSight debug and trace technology was instrumental to the successful bring-up of the Exynos 7870. When designers are working on optimizations to eke out the maximum performance, there is peace of mind in knowing that CoreSight gives the best real-time trace delivering visibility onto the chip fast in order to fine tune the performance" Samsung Exynos 7870


"In addition, ARM CoreSight debug and trace technology was implemented in the chip’s development to provide on-chip visibility that enables fast diagnosis of bugs and performance analysis. Amongst other things, CoreSight ensures it meets the high quality standards required by ISO 26262." Xilinx Zynq-7000

White Papers

Key steps to create a debug and trace solution for an ARM SoC

 Key steps to create a debug and trace solution for an ARM SoC

The global cost of debugging software has risen to $312 billion annually. A new whitepaper: "CoreSight SoC enabling efficient design of custom debug and trace subsystems for complex SoCs", outlines the key steps to create a debug and trace solution for an ARM SoC.


Technical Introduction to ARM CoreSight

Technical Introduction to ARM CoreSight

ARM® CoreSight™ technology is the industry name for debug and trace. This document introduces the concepts which will help you to get the most out of CoreSight. You will learn:

  • Elements of a CoreSight design
  • Processor trace architectures
  • Debug access and DAP topology
  • Typical CoreSight systems

Better trace for better software with ARM CoreSight

Better trace for better software with ARM CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the ARM® CoreSight™ System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, whilst leveraging existing open source trace infrastructures.


Low Pin-count Debug Interfaces for Multi-device Systems

Low Pin-count Debug Interfaces for Multi-device Systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, whilst maintaining support for multi-core systems and interoperability with test.



We use cookies to give you the best experience on our website. By continuing to use our site you consent to our cookies.

Change Settings

Find out more about the cookies we set