CoreSight for Cortex-A Series Processors

Debug

The CoreSight Debug Access Port is a high performance debug access port enabling external debuggers to access cores and internal system busses such memory busses. The DAP provides a combined debug port supporting traditional JTAG and a high performance 2 pin debug interface (Serial Wire Debug)

Trace Macrocells and ETM bandwidth

The CoreSight CPU trace macrocells (ETM and PTM), architected to provide highly compressed real-time trace, enabling developers to observe in real-time the software executed on the processors. The main performance characteristics of the CPU trace macrocells are:

CoreSight SoC Components, Trace Port & ETB Size

The CoreSight SoC components provide a complete SoC level debug and trace solution with low silicon and pin count overheard. All CoreSight SoC components have been architected to support modern SoC design techniques such  multi-power and clock domains and security.
Main performance characteristics of the CoreSight SoC components are:

Trace port size (Trace Port Interface Unit)

By merging all the trace sources in a single trace stream, CoreSight technology enables reducing the number of trace ports to only a single port.

The size of the trace port is a function of the trace bandwidth generated by the trace sources and the nature of the trace, some trace sources create data bursts and may create peak bandwidth leading to a wider trace port.

For reference, benchmarks on Cortex-A9 shows that a 2-bit data trace port running at CPU frequency is in general sufficient to provide in real-time full program trace (non cycle-accurate). This means that a 1 GHz Cortex-A9 processor would need a 4-bit data trace port with a 250 MHz trace clock (DDR)

For detailed benchmarks on trace port for different processors, please contact ARM.

Embedded Trace Buffer (ETB)

When it is not possible to implement a dedicated trace port (e.g. due to severe IO constraints in the final product), traces can be captured on-chip using the CoreSight ETB. Use of the ETB enables high bandwidth trace to capture on the chip. The users based on specific trigger and filter conditions define trace capture.

For detailed benchmarks on ETB sizes for different processors, please contact ARM.

 
For reference, for Cortex-A9 a 4KB ETB can hold trace information for around 125,000 cycles. For multi-processor designs, it is recommended to implement 4KB of ETB memory per CPU.

CoreSight Design Kit for Cortex-A processor family available for licensing:

Getting started with CoreSight

For an overall understanding of CoreSight technology and how to apply CoreSight in your system refer to the CoreSight ™ Technology SystemDesign Guide.

Understanding the CoreSight SoC Components

Refer to the CoreSight SoC page or read the CoreSight™ Components Technical Reference Manual