Rapid Access to Memory
Fastest path from processor to memory
Memory controllers provide fast access between processors and memory. Providing efficient access to shared off-chip memories, including DRAM, critically influences system performance, power and cost. Arm CoreLink Dynamic and Static Memory Controllers deliver best-in-class performance and power for systems with Arm Cortex and Arm Mali processors. Designed, verified and benchmarked in conjunction with Arm processors and AMBA interconnect products, they enable designers of Arm processor-based systems to implement the optimal digital highway for their application.
The CoreLink 500 and 600 series of memory controllers provide best-in-class performance for mobile, consumer and infrastructure systems. Arm CoreLink memory controllers have been deployed by more than 75 licensees, into a wide range of applications including mobile, server, consumer, networking and embedded products. They are closely integrated with CoreLink interconnects and 3rd party DDR PHYs to provide a low risk, high efficiency off-chip memory interface.
The Arm CoreLink DMC-620 Dynamic Memory Controller is specifically designed to provide an optimal memory access solution for SoCs deployed in infrastructure applications such as servers, High-Performance Computing (HPC) and networking. The Arm CoreLink DMC-620 delivers best performance for data transfers from SoC to high-density DRAM memory along with enterprise-class features such as SECDED and symbol-based ECC for x72/x40 DRAM, TrustZone security end-to-end QoS with CMN-600 interconnect.
The CoreLink DMC-520 is specifically designed to provide an optimal solution for enterprise applications including servers and network infrastructure. Enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and End to End QoS are integral components of this new memory controller.
The CoreLink DMC-500 is a system optimized dynamic memory controller that delivers power efficient high performance and access to LPDDR4/3 memory. It is designed to be used in mobile SoCs and provides best-in-class performance per watt metrics. End-to-end QoS for each of CPU, GPU and other bus masters guarantees performance while increasing memory bandwidth utilization, as well as Arm TrustZone technology that provides protected access to memory across the system.