Efficient movement of data across the chip
Massive growth in system integration places on-chip communication and interconnect at the center of system performance. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance. The Arm CoreLink interconnect family from the home of AMBA is the lowest risk solution for on-chip communication. Designed and tested with Arm Cortex and Mali processors, CoreLink interconnect from Arm provides balanced service for both low latency and high bandwidth data streams.
The interconnect improves system performance and reduces power
Arm CoreLink Interconnect provide the components and the methodology for designers to build SoCs based on the AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost.
There are three families of interconnect products:
- CoreLink CMN Coherent Mesh Network and CoreLink CCN Cache Coherent Network - Designed for infrastructure applications.
- CoreLink CCI Cache Coherent Interconnect - Optimized for mobile.
- CoreLink NIC Network Interconnect - Highly configurable for SoC wide connectivity, multiple applications.
Highest performance coherency
The CoreLink CMN Coherent Mesh Network and CoreLink CCN Cache Coherent Network have been designed for intelligent connected systems. They span a wide range of applications including; networking infrastructure, storage, server, HPC, automotive and industrial solutions. They have been optimized with the latest Armv8-A processors and native AMBA 5 CHI interfaces, the industry standard specification for high frequency, non-blocking data transfers. The range of products are appropriate for designs points from 1 to 128 processors.
Highest efficiency coherency
The CoreLink CCI Cache Coherent Interconnect family provide full coherency between the L2 caches of multicore processors including Cortex-A53 and Cortex-A57, and I/O coherency with other masters such as the Mali GPU, sharing data in L2 caches of the processors. For mobile applications hardware managed cache coherency is a fundamental technology for big.LITTLE processing, allowing the operating system to choose the right processor for the right job.
CoreLink CCI Cache Coherent Interconnect offers the smallest and lowest power multi-cluster interconnect:
- CoreLink CCI-550 Cache Coherent Interconnect for best in class performance with Armv8-A processors with improvements in efficiency, performance and scalability
- CoreLink CCI-500 Cache Coherent Interconnect for coherency with up to four clusters including big.LITTLE and coherent accelerators, and higher performance and efficiency with integrated snoop filter
- CoreLink CCI-400 Cache Coherent Interconnect for coherency with up to two clusters (8 cores), essential for big.LITTLE, also applicable to low-cost infrastructure
Highly configurable interconnect
The CoreLink NIC Network Interconnect family offers a low-power, low latency rest of SoC interconnect. It can be tailored to suit your system requirements, and are widely licensed across many applications, from Cortex-M based microcontrollers to Cortex-A based powerful SoCs. It is a fully configurable, hierarchical connectivity for AMBA that can be optimized using the latest Arm IP Tooling.