CoreLink System Memory Management Unit

The ARM® CoreLink™ System MMU provides memory management services to SoC bus masters to complement those provided by the Cortex®-A series processor family. The MMU performs translation, protection and isolation functions for IO components in an SoC with a common view of memory.


CoreLink MMU-500 Memory Management Unit

The CoreLink MMU-500 extends processor virtualization to other bus masters in the system with hardware accelerated stage 1, stage 2 and nested stage 1/2 address translation using distributed Translation Look-aside Buffers (TLBs). CoreLink MMU-500 is compatible with the ARMv8-A enabled Cortex-A72 and Cortex-A53 processors, and is backwards compatible with the ARM Cortex-A15 and ARM Cortex-A7 processors. The TLBs are controlled with a single Translation Control Unit (TCU) which performs the Page Table Walk (PTW) to memory upon a translation miss. This offers maximum flexibility in implementing efficient SoC designs that need to support virtualized applications.

The ARM CoreLink MMU-500 provides:

  • ARMv7 and ARMv8 page table support, adding 64K granules for stage 1 (VA->IPA) and stage 2 (IPA-PA) translations to improve hypervisor efficiency
  • Large input address range to cover 32 bit or 64 bit VA input (stage 1) and 48 bit IPA input (stage 2)
  • Large output address range to cover up to 48 bit IPA (stage 1) and 48 bit PA (stage 2)
  • Support for up to 128 device contexts (stream IDs)
  • Distributed TLBs supporting up to 32 different IO devices per TCU to increase TLB efficiency and to save area and power
CoreLink MMU-500 in an example premium mobile SoC
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CoreLink MMU-401 Memory Management Unit

The CoreLink MMU-401 extends processor virtualization to other bus masters in the system with hardware accelerated stage 2 address translation. It is compatible with the ARM Cortex-A15 and Cortex-A7 processors and offers stage 2 translation for bus masters that already implement MMU functionality for stage 1 translation, such as the Mali-400 Graphics Processor. MMU-400 helps to reduce the hypervisor overhead in managing complex bus master interactions.


Customer Successes

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"The ARM CoreLink MMU-500 System Memory Management Unit enabled APM to quickly integrate an architecturally compliant and proven design into the class leading ARM 64b X-Gene processors allowing our design team to focus on developing differentiated IP. We have been very pleased with the quality of the design and the support provided by ARM." -Gaurav Singh, VP Technical Strategy, Applied Micro

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"Along with the complete Layerscape architecture, the flexibility of the ARM CoreLink System MMU-500 Memory Management Unit, which maps virtual addresses to physical ones, enables the virtualization that makes the network more agile and serviceable." - Freescale press release


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