The CoreLink MMU-500 is compatible with the ARM Cortex-A50 family of processors, consisting of the ARM Cortex™-A57 and Cortex-A53 processors, and is backwards compatible with the ARM Cortex-A15 and ARM Cortex-A7 processors. It offers nested stage 1 and stage 2 accelerated address translation with multiple distributed translation buffers controlled from a single control unit to be compatible with a wide range of bus master types and capabilities. This offers maximum flexibility in implementing efficient SoC designs that need to support virtualized applications.
The CoreLink MMU-400 is compatible with the ARM Cortex-A15 and Cortex-A7 processors and offers stage 2 accelerated address translation for bus masters that already implement MMU functionality for stage 1 translation, such as the Mali-400 Graphics Processor, to reduce the hypervisor overhead in managing complex bus master interactions.
A number of virtualization use cases are outlined in an ARM System MMU Virtualization whitepaper.