ARM® CoreLink™ AMBA® System Controllers is a collection of controller IP offered by ARM. These controllers are for DMA, Level 3 Cache, TrustZone®, and Peripherals. They are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with ARM processors, multimedia and System IP, they are the natural complement to the Interconnect and Memory Controller product lines.
The Direct Memory Access Controller (DMAC) is a hardware feature that enables movement of blocks of data from peripheral to memory, memory-to-peripheral or memory-to-memory. This movement of data by a separate entity significantly reduces the load on the processor.
AMBA DMA Controllers for AXI and AHB
DMA Controllers can have a significant impact on both system performance and system power. It is critical that the design provides for optimum compatibility with the bus architecture (AMBA) and provides the flexibility required to support a wide range of system requirements.
ARM delivers DMA controllers for both high-end, high-performance AXI systems based on the Cortex®-A and Cortex-R families and cost-efficient AHB systems built around Cortex-M and ARM9 processors.
DMA in high-performance AXI systems
The AMBA AXI-based PrimeCell® DMA Controller, CoreLink DMA-330, is a highly flexible, high-performance DMAC designed to provide maximum configurability and programmability. Configurability optimizes the gate count for target systems. The size can be as low as 40K for low-end configurations. The DMA-330 also provides a natural migration path for users of the AMBA AHB based DMA Controller, PL080.
An FSM based DMAC can provide only limited functionalities as the gate count increases rapidly with the increase in the number of features supported. In contrast, the DMA-330 is a micro-programmable DMAC, with its own instruction set, and provides a rich set of features while keeping the gate count low. The DMA-330 instruction set design provides flexibility for programming DMA transfers. The program code is stored in system memory that the DMAC accesses using its AMBA AXI interface and the DMA-330 uses an efficient caching system to optimize performance and minimize bus traffic.
DMA in cost-effective AHB systems
For AHB systems based around the Cortex-M™ processors ARM delivers the CoreLink DMA-230 "micro" DMA controller. Designed for very low gate count and low power operation DMA-230 provides a flexible, high-performance DMA Controller required by such designs.
AMBA DMA Controller Performance
The DMA-230 and DMA-330 DMA Controllers are highly configurable. Therefore, power, performance and area will depend on configuration.
- DMA-230 is designed for very low area, typical configurations are 3K-10K gate.
- DMA-330 is designed for high performance
CPU to off-chip memory communication has become the performance bottleneck in many SoC.
Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip.
AMBA Level 2 Cache Controllers are either embedded in the CPU or delivered as standalone components. They are designed alongside the CPU to match the processor's requirements and easily integrate into AMBA AXI or AHB interconnects.
AMBA Level-2 Cache Controller designs boost performance of AMBA AHB and AXI processors while reducing overall traffic to system memory and therefore SoC energy consumption. The L2C-310 is a high performance AXI level 2 cache controller designed and optimized to address ARM processors using the AXI interface.
L2C-310 for AMBA AXI processors
The CoreLink L2C-310 is a high performance AMBA AXI level 2 cache controller architected to optimize all AMBA AXI-based processors. The L2C-310 is a mature IP, widely licensed with the Cortex-A9 and Cortex-A5 processors and others ARM AXI processors, ARM demonstrated L2C-310 operating at 2Ghz part of the Cortex-A9 hard macro implementations.
While architected to deliver optimal performance with ARM AXI processors, L2C-310 can operate with any AXI masters and therefore re-use across many platforms.
TrustZone on-chip memory
- TrustZone Boot ROM, 8-16KB for signature check code
- On-chip memory (e.g. TCM) – 2KB instruction and 100 bytes data for Secure Monitor
- On-chip RAM for secure code and data. TrustZone Internal Memory Wrapper (PL141) can partition a single larger on-chip RAM into Secure and Non-Secure) Worlds
TrustZone off-chip memory
- TrustZone RAM - in DDR memory, typically 256K-1M for decrypted/checked code.
- Off-chip memory cheaper per bit
- Partitioning a single off-chip memory in up to 16 secure regions by TrustZone Address Space Controller (TZC-380). Resistant to software attack.
ARM offers a number of APB Peripherals to assist designers build complex SoCs as quickly as possible. These products are designed and validated to the highest of standards, support the broadest range of industry tools and offer excellent value for money.
PL011 Synthesizable UART
PL022 Synthesizable Single-wire Peripheral Interface (SPI) controller (master and slave) that supports Motorola SPI, TI SSI and Microwire.
PL050 Synthesizable keyboard or mouse interface complying with IBM-defined PS/2 interface standard
PL061 Synthesizable GPIO controller supporting 8 bits with interrupt control.