CoreLink Interrupt Controllers

The ARM® CoreLink™ Multi-Cluster CPU Interrupt Controller portfolio contains a range of interrupt management solutions to suit all Cortex® processor systems. Each controller provides unified interrupts for complex processors.

CoreLink GIC-500 Generic Interrupt Controller

The CoreLink GIC-500 is a scalable interrupt management solution that eases the virtualization process. CoreLink GIC-500 implements the GICv3 architecture and is designed to support multiple clusters of ARMv8 processors such as the ARM Cortex-A72, Cortex-A57 or Cortex-A53 processors up to a maximum of 128 processors. It manages up to 960 shared peripheral interrupt signals and virtualizes message-based interrupts such as PCIe MSI(-X) using interrupt translation services. The GIC-500 uses affinity level routing for large scalability. This can be consolidated as one monolithic block or as a network of discrete re-distribution blocks to suit SoC size and layout. Message-based interrupts may be sent directly to any re-distributor block in the affinity tree. Additionally GIC-500 also provides support for private peripheral and software-generated interrupts.


GICv3 architecture

CoreLink GIC-500 is an ARM implementation of the latest GICv3 architecture spec. Some of its updates include:

  • Support for up to 128 cores in maximum of 32 clusters
  • Support for message-based interrupts
  • Enhanced security model
  • System register access
  • Vastly expanded interrupt ID space
  • Support for legacy operation giving compatibility with GICv2
  • TrustZone support
  • Support for interrupt translation services for virtualization
There are a number of new innovations in the GICv3 architecture that offer a scalable infrastructure for the interrupt handling of larger systems. The changes help manage a larger core count, reduce message congestion and provide a more efficient way for interrupts to be handled across SoCs. The ARM CoreLink GIC-500 is an interrupt controller designed by ARM that harnesses all of the benefits of the GICv3 architecture to improve interrupt efficiency and allow for virtualization on-chip.
CoreLink GIC-500 implemented in an example enterprise SoC
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CoreLink GIC-400 Generic Interrupt Controller

The CoreLink GIC-400 detects, manages, virtualizes and distributes up to 480 interrupts between up to 8 CPUs in Cortex-A15 and Cortex-A7 multicore clusters. You can configure the GIC-400 to support only the required number of CPUs and interrupts to reduce gate count.

The GIC-400 implements GICv2 Architecture, Security and Virtualization Extensions ARM IHI 0048B.


Customer Successes

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"On-chip virtualization is supported by the CoreLink MMU-500 system memory management unit and the CoreLink GIC-400 generic interrupt controller. Finally, as security from attack and content protection become increasingly relevant in system design, the Kirin 950 made use of the TZC-380 TrustZone™ address space controller to support the ARM TrustZone system-wide approach to security by protecting selected memory regions and peripherals such as screens and keypads." HiSilicon Kirin 950

Default Headline

"With the Tri-Cluster architecture running different tasks simultaneously, the complexity of managing interrupts increases significantly. The CoreLink GIC-500 generic interrupt controller used affinity level routing to manage the increase in scale in a simple and efficient manner. This boosts processor efficiency, leading to some of the power improvements in the new chip." MediaTek Helio X20


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