CoreLink Controllers for Memory, Cache, DMA, TrustZone ® technology and Interrupt Handling
System Memory Management UnitThe CoreLink MMU-500 Memory Management Unit extends hardware-assisted virtualization of the Cortex™-A57, Cortex-A53, Cortex-A15 and Cortex-A7 hypervisor mode across the entire SoC. The MMU-500 translates to physical addresses defined by its TLB that reflects the current CPU context to ensure other masters use consistent memory mapping. Fitting the MMU-500 means drivers no longer require porting for the hypervisor using para-virtualization and raises performance through saving the large para-virtualization software overhead.
A number of virtualization use cases are outlined in an ARM System MMU Virtualization whitepaper
CPU to off-chip memory communication has become the performance bottleneck in many SoC. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters.
Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip.
CoreLink Level 2 Cache Controllers, embedded in the CPU or delivered as standalone components, are designed alongside the CPU to match the processor's requirements and easily integrate into AMBA AXI or AHB interconnects.
Efficient use of DMA can significantly improve system performance in multiple dimensions. For example, using a DMA controller can offload a CPU thereby either reducing power or boosting CPU performance (or a combination of both).
The AMBA DMA Controllers have been designed to complement both high-end and energy efficient systems. They provide a centralized DMA processing capability that is high performance and highly flexible while at the same time area efficient.
AMBA Interrupt Controllers provide an efficient implementation of the ARM Generic Interrupt Specification to work in multi-processor systems with AHB or AXI interfaces. They are highly configurable to provide the ultimate flexibility in handling a wide range of interrupt sources that can control a single CPU or multiple CPUs.
Three system IP blocks to support the ARM TrustZone system-wide approach to security in preventing access by malicious software to memory regions and peripherals such as keyboards and screens:
- TrustZone Address Space Controller (TZC-380) to protect code/data in external memory regions
- TrustZone Protection Controller (BP147) controls the security status of peripherals
- TrustZone Internal Memory Wrapper (BP141) manages a secure region within the on-chip memory
A 64-bit Color LCD Controller (PL111) supporting AHB master and slave interfaces and driving TFT, STN, single and dual panel displays.