CoreLink Verification & Performance Exploration tool

Features Summary

• AXI Monitor, AXI Master, AXI Slave components fully supporting the AMBA 3 AXI protocol
   
• Traffic Profiling toolkit GUI (TPT) to generate & view traffic profiles
   
• Includes Comprehensive AXI coverage points and AXI protocol checker in OVL and SVA formats

Benefits Summary

• Provides both an AXI™ performance verification and a functional verification tool in one
   
• Gives a measured 300x performance boost over conventional functional verification IP
   
• Abstract away as much or as little of a system as required by attaching VPE-301 components to any AXI connection within a system
• Is faster than developing a cycle-accurate System-C model for generating representative bus traffic
   
• Is more accurate than Excel in that VPE-301 animates benchmarking data to bridge the gap between spreadsheet analysis and slow RTL simulation

Main VPE-301 Components

VPE-301 components contain user interfaces that enable you to access different levels in the AXI protocol stack, such as transaction, channel, and RTL signal levels. VPE-301 contains AXI master, AXI slave, and AXI monitor components that you can use for:

• Functional verification by using directed vectors and TLM access to an AXI bus using a SystemVerilog interface.
   
• Performance exploration by using the TPT to analyze captured statistical traffic profiles to modify and create new profiles for replay.

In this way, VPE-301 enables you to quickly identify and test system-level optimizations and opportunities for improvement. VPE-301 also contains an AXI protocol checker that contains OVL and SVA assertion libraries ensuring adherence to  AXI protocol. 

Algorithmic traffic generation

VPE-301 Masters and Slaves provide an optional Transaction Level Modeling (TLM) interface. This is a high-level interface that you can extend using SystemVerilog. You can develop your own algorithmic code at the transaction level using the TLM interface with SystemVerilog. You can create function calls to a set of functions that VPE-301 provides to enable you to develop tests quickly. VPE-301 performs the randomization of the traffic and the full protocol stack. You can add timing to the algorithmic code to represent a different type of micro-architecture.

Statistical profiled traffic generation

Statistical profiled traffic generation is derived from:

• The concept of constrained random generation
   
• Telecommunications models.

Traffic profiles statistically characterize the traffic, or transactions, on an AXI connection and represent IP traffic. Traffic flows are identifiable streams of traffic, or AXI transactions, between two points in a system, and represent the different streams or threads that the device issues. VPE-301 extends the concept of constrained random verification and applies this at the system level by adding mathematical modeling from the telecommunications industry.

You can define traffic profiles:

• By using the GUI in the TPT 
   
• By capturing them from a simulation.

The Traffic Profiling Toolkit (TPT)

You can use the TPT to: 

• Create or adapt profiles
   
• Analyze AXI traffic 

The traffic profile below shows and example of a profile populated by the VPE-301 monitor component with timing statistics from both read and write channels. The ITT histogram for example in the WRITE flow for device ID0 is showing the distribution in number of cycles between each write transaction. The first READ flow histogram for device ID0 is showing the distribution of read-initial-latency values in cycles. These are just two histograms from a wide range of available histograms covering all aspects of the AXI protocol.

You can create multiple flows in a profile, and characterize them by any payload parameter such as ID, or by attributes such as the address ranges accessed.

At this point, the traffic profile is retainable for analysis purposes or reusable in a VPE-301 Master or Slave component to define the shape of transactions and responses generated in the bus. Further fine-tuning can be applied to any histogram such as changing distribution of bursts, burst types, address ranges, etc., in order to answer what-if performance questions relating to the system or device under test. 

Further analysis is possible on sampled traffic profiles, with the example below showing the analysis view tab within the TPT.The example below highlights bandwidth in MB/s from each master as well as number of data transfers.
 

Along with the analysis histograms shown above, the following analysis features are also provided as standard:

• Data bus utilization
   
• Read and write flow transfer latency summaries 
   
• Profile payload summaries 
   
• Read and write flow payload summaries. 
   

VPE-301 and ARM CoreLink system IP products:

Along with the ability to monitor or drive any standard AMBA AXI3 interface, VPE-301 is also compatible with the following ARM System IP products:

NIC-301 and VPE-301

Once a NIC-301 component has been configured and rendered using ADR-301, VPE-301 components can be instantiated onto each of its AXI interfaces for the purposes of performance exploration. Please see the VPE-301 product on this page for further details.

Downloads

The AMBA 3 AXI Protocol Assertions are available to registered ARM customers.

User Guides

AMBA3 AXI Protocol Checker User Guide

White papers

Traffic management for optimizing media intensive SoCs