Accelerating AMBA Protocol-Based Design
Configuring and stitching together complex IP components manually is a time consuming process, which in turn introduces further complexity when ensuring the compatibility of interface parameters such as write interleaving and acceptance depths, bus widths, ID widths etc.
The ADR-301 tool provides a single common front end for configuring and integrating System IP and other ARM IP. The main benefits from this approach comprise rapid, error free configuration using intelligent configuration tools, and correct by construction connection of ports using the IP-XACT interface standard.
ADR-301 outputs configured Verilog RTL along with industry standard IP-XACT descriptions for ease of integration into third party design and implementation tools. Once a component is generated it can also be added to the ADR-301 component library to maximize re-use. Stitching together of multiple components is supported in a hierarchical manner.
Comprehensive Set of Features Provided
|Configuration Engines for System-IP which employ designer knowledge||Rapid configuration of ARM AMBA components. Automatic checks for non-optimal and mutually exclusive configuration options always resulting in 'valid' configurations|
|GUI drag and drop integration environment||Rapid assembly of configured AMBA components.|
|Industry standard IP-XACT 1.2 and 1.4 support||
Maximizes re-use of existing configurations by allowing the user to create an IP library. Supports assembly and 'stitching' of ARM components and export of hierarchical components for the purpose of IP-XACT based top-level Verilog generation/stitching.
Outputs generated from ADR-301
From an IP Configuration Engine
- A human-readable, fully commented set of optimized Verilog RTL modules
- A test bench environment capable of demonstrating an 'out of box test' of the configured RTL module
- An IP-XACT file representing the component instance that has been configured
Note: Although ADR-301 ships with all configuration engines, System IP is licensed separately from ADR-301 and requires a simple linking step during IP installation to enable RTL generation
From IP-XACT stitching
- A top level Verilog file
- A .VC file containing all of the Verilog module references
- An IP-XACT file that can be used to start the stitching process at the next level of hierarchy