Advanced AMBA 3 Interconnect IP (PL301) As SoC complexity increases, the importance of a combined link from multiple masters to memory becomes increasingly important. To address the challenges of high performance design requires an end-to-end solution to this growing fabric challenge. On-chip interconnect is one part of the puzzle. From a technology perspective, AMBA 3 AXI provides the means to perform low latency, high bandwidth on-chip communication between multiple masters and multiple slaves. Moving one stage further, from an implementation perspective, configurability and programmability are becoming vital to ensuring IP can be tuned for a given application and/or project requirement. ARM's latest interconnect solution (PL301) has been developed to scale between ultra efficient systems right the way through to the highest performance solutions AMBA based communication finds itself applied in. For example AMBA 3 AXI is increasingly used in the following applications: Mobile (cell phones, PDA's, portable gaming devices) Automotive (console entertainment, engine management systems) Enterprise (high end printing, networking) Home (Digital entertainment, tethered gaming, WiFi)
Moreover, PL301 has been developed to work as part an optimized backplane. A good example being the Quality of Service (QoS) scheme implemented in both the AMBA 3 AXI interconnect (PL301) and the AMBA 3 AXI dynamic memory controller (PL340) - ensuring run time defined masters can enjoy bandwidth prioritisation to off chip memory. PL301 is a highly complex IP generation technology, this is a trend that will be seen to accelerate in future as design requirements continue to evolve. There is scope for far greater optimization than would traditionally possible. To help manage this, ARM have developed an IP automation solution called AMBA Designer. AMBA Designer is used to ensure the design space is both efficiently and correctly explored for the appropriate Fabric PrimeCell IP. By combining design automation with highly configurable IP solutions like the PL301, design teams can explore architectures quickly and produce optimized Verilog RTL for implementation in minutes. Key Features of the P301 Advanced AMBA 3 Interconnect include: Full AMBA Designer integration Configurable number of master and slaves Configurable master/slave protocol interfaces (AXI, AHB, APB) Configurable frequency crossing (synch up, synch down, asynch) Configurable data and address width Dynamic programmable Quality of Service (QoS) for performance Sparse connect area optimization Various configurable pipping capabilities for performance Comprehensive set of cyclic and arbitration schemes Security support for TrustZone
Speed
The PL301 generates a combinatorial data path to minimize latency in the system. The speed at which the data can be moved depends on the timing characteristics of the masters and slaves. Register slices can be added on the periphery of the multi-layer interconnect to isolate long timing paths or to pipeline the inter-connect to considerably increase the system speed. Efficiency
The interconnect efficiency is boosted by interleaving the read and write data from different threads, so that latency from one transaction does not impact the performance of data from other threads. The PL301 manages the data through the use of ID tags to ensure that this process is transparent to the system and that deadlock hazards are avoided. The system architect can evaluate the various cyclic and arbitration schemes to find the optimum implementation for performance/area. Layered above arbitration is the QoS scheme that can be configured and the reprogrammed as required during run time, thereby inserting bandwidth (service) improvement for specific master. Flexibility
The system architect can choose one extreme of a single multi-layer interconnect, providing the maximum run-time flexibility for running multiple applications on a single platform. Alternatively, the designer can choose to construct the system through a hierarchy of multi-layer structures. This ensures the maximum speed key data paths (such as between the processor and external memory), while minimizing the interconnect size. Remap pins allow the system to change the memory map dynamically. The typical application for this would be during the power-up phase of the system where the initial program code is stored in ROM. Security
The AXI interface protocol offers support for en-forcing system security at the hardware level. The PL301 uses information identifying whether a peripheral is secure, and uses this to ensure that the peripheral is inaccessible to non-secure transactions. This, in conjunction with a secure-aware processor, such as the TrustZoneTM-enabled ARM1176JZ(F)-S, forms a key element in building a secure system. Licensing model
The PL301 is available for single-use or multi-use licensing with no royalty fee. Back to Top | 
