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SC300 Processor

SC300 Processor Image
The SecurCore™ SC300™ processor provides the most secure and energy efficient solution to meet challenging design goals for both contact and contactless operation, whilst at the same time delivering high performance. The SC300 processor is based on the ARM Cortex™-M3 processor, leveraging its excellent mix of architectural features, high performance and very low costs. It uses the Thumb®-2 instruction set, delivering 32-bit high performance at 16-bit levels of code density.
 


The SC300 processor is based on the ARM Cortex-M3 processor, leveraging its excellent mix of architectural features, high performance and very low costs. It uses the Thumb-2® instruction set, delivering 32-bit high performance at 16-bit levels of code density.

The SC300 processor includes a configurable Nested Vector Interrupt Controller (NVIC) for highly deterministic and low interrupt latency, crucial for running multiple security algorithms and communication interfaces concurrently.

With its highly advanced debug features and standardized peripheral models, the SC300 processor helps OEMs to  reduce drastically software development overheads by easing code portability and reusability with the resultant time-to-market significantly reduced.


Leading Power Efficiency

With high performance and low dynamic power consumption, the SC300 processor delivers leading power efficiency. Coupled with integrated sleep modes and optional state retention capabilities, the SC300 processor ensures there is no compromise for applications requiring low power and strong performance.


Performance DMIPS/MHzOutstanding Performance

Based on a 3-stage pipeline optimized for executing directly from flash memory, the processor delivers outstanding efficiency in real world applications.

The processor executes Thumb-2 instruction set for optimal performance and code size, including hardware division, single cycle multiply, and bit-field manipulation.

 


Tightly Integrated Interrupt Handling

The SC300 processor integrates the Nested Vectored Interrupt Controller (NVIC) to deliver exceptional response to interrupts. The NVIC is highly configurable at design time to deliver up to 240 system interrupts with individual priorities, dynamic reprioritization and integrated system clock.


Simple Programming Target

With all exception handling executed in hardware the processor removes the need to program in assembler code, provides an excellent platform for C code, and significantly accelerates development time.

 


 

 

Ecosystem

Over 650 members in the Connected Community supporting the Cortex-M3 based SC300

  • Broadest ecosystem of compilers, debuggers and RTOS tools in the industry
  • Plentiful design services partners to aid in design task
  • Large variety of third party IP available to integrate with processors

SC300 (Cortex-M3) Performance, Power & Area

 

 TSMC 180nm G

TSMC 90nm G

Speed Optimized   

Area Optimized 

Speed Optimized   

Area Optimized   

 Standard Cell Library  ARM SC7  ARM SC7  ARM SC9  ARM SC9
 Performance (Total DMIPS)  125 75 340 75
 Frequency (MHz)  100 50 275 50
 Power Efficiency (DMIPS/mW)  3.75 6.35 TBD 12.5
 Area (mm2)  0.37 0.25 0.083 0.047

 

Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Physical IP standard cell libraries and RAMs. Area numbers include the CM3Core, the Nested Vectored Interrupt Controller (NVIC) and Bus Matrix.

The speed-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

Frequency and Area measured for worst case conditions – 0.18µm process - 1.62V, 125C, slow silicon ; 0.13µm process - 1.08V, 125C, slow silicon

Power measured for typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ; 0.13µm process - 1.2V, 25C, typical silicon.


 SC300 Features

 Architecture  ARMv7-M (Harvard)
 ISA Support  Thumb® / Thumb-2
 Pipeline  3-stage + branch speculation
 Dhrystone  1.25 DMIPS/MHz
 Memory Protection  8 region MPU with sub regions
 Interrupts  NMI +1 to 240 physical interrupts
 Interrupt Latency  12 cycles
 Inter-Interrupt Latency  6 cycles
 Interrupt Priority Levels  1 to 255
 Sleep Modes  Integrated WFI and WFE Instructions. Sleep & Deep Sleep Signals
 Bit Manipulation  Integrated Instructions & Bit Banding
 Enhanced Instructions  Hardware Divide (2-12 Cycles) & Single-Cycle (32x32) Multiply.
 Debug (Removable)  JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints

 

The SC300 processor has several security features that make it an ideal choice for tamper resistant smartcards. Further details on the security features are available under an NDA (non-disclosure agreement) from ARM.


System Development

The SC300 processor includes AMBA® interconnect compatibility for fast and efficient system design with peripherals and memories

 

Product

Description

 AMBA

AMBA System IP and design tools provide the components and methodology for designers to build SoCs that maximize the efficiency of data movement and storage, enabling high performance at the lowest power and cost.

AMBA Design Kit (ADK)

Enable fast configuration of embedded systems containing Cortex-M series processors with an AMBA AHB interface

AHB Memory Controllers

For AMBA AHB-based systems ARM provides the PL24X family of dynamic, static and hybrid memory controllers

AHB Peripherals

PL011 Synthesizable UART
PL022 Synthesizable Single-wire Peripheral Interface (SPI) controller
PL050 Synthesizable keyboard or mouse interface complying with IBM-defined PS/2 interface standard
PL061 Synthesizable GPIO controller supporting 8 bits with interrupt control.

Tools Ecosystem

Full support from RealView® Microcontroller Development Kit (the Keil uVision environment), the most popular smart card development tool chain in the industry


 
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