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Hard Macro Processors

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The ARM Hard Macro portfolio offers performance and power optimized hard macrocell implementations of the Cortex™-A series processors. For SoC designers looking to make a trade-off between the multifaceted flexibility offered by the traditional RTL based SoC development strategy and the significant costs and efforts it involves, the ARM Hard Macro portfolio is an exciting alternative that enables higher profitability through benchmarked PPA (Performance, Power, and Area), design risk reduction and faster time to market. 

                              

 


While soft-core implementation remains the best choice for design teams wanting complete freedom and flexibility, recent industry trends are making designers look at alternatives such as using ARM Hard Macros.  

ARM Hard Macros enable vendors to achieve higher levels of innovation and profitability by facilitating device differentiation and highly competitive solutions. ARM Hard Macros are also an attractive choice for designers new to the ARM architecture or those wishing to migrate upwards to Cortex-A from ARM9 and ARM11 based designs.  

Tapping into our vast pool of ARM processor, tools and implementation knowledge and experience, ARM Hard Macros provide finely tuned PPA results that are hard to beat using the traditional soft-core implementation strategies for all but the most experienced design teams.

Design Challenges and Industry Trends Hard Macro Features & Benefits

Increasing SoC Complexity 
SoC complexity has increased over the last few years, with many SoC now featuring dual or quad cores.

Design Simplification 
ARM Hard Macros offer significant design simplification and risk mitigation.
Time to Market Pressure
Vendors face massive challenges, with high rewards for early market penetration, but crippling consequences for project delays.
Fast Time to Market with differentiated products
ARM Hard Macros offer an assured and verified solution, allowing vendors to focus on key capabilities and differentiation.
Market Driven PPA Pressures
Designers face high pressure to hit PPA sweet spots. Getting the PPA balance right requires skill and experience with mixed Vt design, DFT/DFM, power gating etc.
PPA Assurance & Integrated Design
ARM Hard Macros offer a highly optimized and assured PPA in an integrated design that includes processor IP, POP, power domains, clock tree insertion, DFM/DFT and more in one package.
Cost and Risk Barriers 
The high costs and risks associated with adopting new technology or entering new markets does inhibit some vendors.
Low Cost, Low Risk
ARM Hard Macros significantly lower the total cost of ownership and design risks offering vendors an easy, low cost, reduced risk route to market success.

     


The ARM Hard Macro portfolio currently consists of the Cortex-A5, Cortex-A9 and Cortex-A15 processors.

ARM Cortex-A5 Single-core 40LP Hard Macro

The smallest, lowest power ARMv7 CPU capable of reaching over 1GHz

The Cortex-A5 UP (Uni-processor) Hard Macro is the first licensable 1GHz capable Cortex-A5 processor implementation in TSMC 40LP. Today’s users are increasingly accustomed to the rich multimedia and internet experience offered by leading smart phones and tablets. The demand for these features and user experiences is driving a wide range of next generation value devices from low cost handsets and feature phones to pervasive embedded, consumer and industrial devices. The Cortex-A5 UP hard macro provides a high performance, low cost solution enriching tomorrow’s value devices with high-end graphical user interface, multimedia, internet browsing and security capabilities through the integrated FPU, NEON™ and TrustZone® features.


ARM Cortex-A9 Dual-core 40G Hard Macros

2GHz Capable Cortex-A9 Dual-Core Processor Implementation

The Cortex-A9 dual-core hard macro implementations on TSMC 40G process enable silicon manufacturers to have a rapid and low risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices for the consumer and enterprise market. The hard macro is available as two variants – speed optimized and power optimized. The Cortex-A9 speed-optimized hard macro incorporates aggressive low-power techniques to extend further ARM performance leadership into high-margin consumer and enterprise devices within the power envelope necessary for compact, high density and thermally constrained environments. This implementation operates in excess of 2GHz when selected from typical silicon and represents an ideal solution for high-margin performance-oriented applications. Power Optimized In applications where energy efficiency is of paramount importance, the Cortex-A9 power-optimized hard macro implementation offers an attractive mix of performance and low power, capable of operation at 800MHz under a tight power budget.    

ARM Cortex-A9 Dual-core 40LP Hard Macro

Performance optimized Cortex-A9 Dual-Core Processor Implementation

This implementation is optimized to obtain the best performance on the low power TSMC 40LP process. Ideally suited to SoCs operating within a tight power budget, yet wishing to provide a high level of performance and functionality, this hard macro is capable of delivering 1GHz+ performance. The implementation builds upon the inherent low power capabilities of TSMC40LP process through a strong design focus on reducing leakage and dynamic power while maintaining high performance levels.


ARM Cortex-A15 MP4 Quad-core 28HPM Hard Macro

Capable Cortex-A15 Quad-Core Processor Implementation

The ARM Cortex-A15 quad-core hard macro is capable of delivering more than 2.0GHz on a TSMC 28HPM process. The low leakage implementation, featuring integrated NEON SIMD technology and floating point (VFP), delivers an extremely competitive balance of performance and power and is ideal for wide array of high-performance computing applications for such as notebooks through to power-efficient, extreme performance-orientated network and enterprise devices.

ARM Cortex-A15 MP2 Dual-core 28HPM Hard Macro

Delivering exceptional power efficiency for Cortex-A15 based handheld devices

The ARM Cortex-A15 dual-core hard macro provides exceptional efficiency and is capable of delivering up to 10,000 DMIPS within a mobile power envelope on a TSMC 28HPM process.
The low leakage 9 track implementation, featuring integrated NEON™ SIMD technology and virtual floating point (VFP), includes a 1MB level 2 cache to deliver an extremely competitive balance of performance and power and is ideal for wide range of power-sensitive handheld devices such as mobile phones, tablets and devices such as single board computers that are used across a wide array of applications.


ARM Hard Macros are available in a number of different implementation options with more being added.

Currently the following options are available.                      

  Process
Processor TSMC
40LP 
 TSMC
40G 
TSMC
 28HPM
Cortex-A5 Single-core  X     
Cortex-A9 Dual-core X
Cortex-A9 Dual-core X    
Cortex-A15 Quad-core X
Cortex-A15 Dual Core     X


ARM Hard macro processors incorporate and are supported by a broad range of ARM technology including  Physical IP and development tools. This technology is complemented by a broad range of SoC and software design solutions, tools and services from the ARM Connected Community™ to provide ARM Partners with a smooth path through the development, verification and production of full function, compelling devices while significantly reducing time-to-market.

Physical IP

ARM Hard Macros are based upon a set of high performance POP™ IP containing advanced ARM Physical IP for 40nm and 28nm technologies to enable rapid development of leadership physical implementations. ARM is also working early to assure a roadmap to 20nm optimizations.

POP IP supports ARM strategy of offering specifically targeted Physical IP to enable Partners to achieve tuned implementations of ARM cores. ARM is uniquely able to design the optimization packs in parallel with the Cortex processor architecture, enabling the processor and physical IP combination to deliver workstation class performance in a mobile power envelope while facilitating rapid time-to-market.

POP IP is composed of three elements necessary to achieve an optimized ARM core implementation.

  • First, it contains ARM Artisan® Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology. This Physical IP is developed through a tightly coupled collaboration with ARM Processor Division engineers in an iterative process to identify the optimal results.
  • Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation.
  • Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.

Tools Support

All ARM processors are fully supported in the ARM Development Suite 5 (DS-5™) tool suite, as well as a wide range of third party tools, operating systems and EDA flows. 

ARM DS-5 software development tools are unique in their ability to provide solutions that take full advantage of the complete ARM technology portfolio. The ARM Development Studio 5 (DS-5™) provides a complete range of software tools to create, debug and optimize systems based on the Cortex-A15 MPCore processor. It incorporates the DS-5 Debugger, whose powerful and intuitive graphical environment enables fast debugging of bare metal, Linux and Android native applications. In addition, its new ARM Streamline™ Performance Analyzer simplifies the identification of hot spots in software and load balancing between cores. Early software development before silicon availability is enabled by the ARM Compiler, and an ARM Versatile™ Reference Virtual Platform built on ARM Fast Models technology. This Virtual Platform is available for a free 6-month evaluation.


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