Cortex-R7 Processor

The Cortex™-R7 processor provides a high-performance dual-core, real-time solution for a vast range of deeply embedded applications. The Cortex-R7 processor brings much higher levels of performance to the Cortex-R series of processors through the introduction of new technology including out-of-order execution and dynamic register renaming, combined with improved branch prediction, superscalar execution capability and faster hardware support for divide and other functions.

Why Cortex-R7?

Performance

Specifications

Related Products

Resources

The Cortex-R7 processor is the highest performing Cortex-R series processor.

The Cortex-R7 processor was designed for implementation on advanced silicon processes from 65 nm down to 28 nm and beyond with an emphasis on improved energy efficiency, real-time responsiveness, advanced features and ease of system design. On a 40 nm G process the Cortex-R7 processor can be implemented to run at well over 1 GHz when it delivers over 2,700 Dhrystone MIPS performance.

The processor provides a flexible local memory system that supports Tightly Coupled Memory (TCM) local shared memory and a peripheral port, enabling SoC designers to reach demanding hard real time requirements within constrained silicon resources.

Cortex-R7 Performance Power and Area

Processor area, frequency and power consumption are highly dependent on process, libraries and optimizations. The table below estimates a dual processor implementation of the Cortex-R7 processor on a mainstream process technology with high-density, standard-performance cell libraries and RAMs.

Dual processor systems	28 nm	65nm LP
Clock frequency	1GHz est.	360MHz est.
Performance (DMIPS)	4,600 est.	1650 est.
Total area (sq mm)	1.7 est.	5.3 est.
Power efficiency (DMIPS/mW)	> 11 est.	> 5 est.

Cortex-R7 Processor

Feature	Description
Microarchitecture	Eleven-stage pipeline with instruction pre-fetch, branch prediction, superscalar and out of order execution and register renaming. Parallel execution paths for load-store, MAC, shift-ALU, divide and floating point. 2.53 Dhrystone MIPS/MHz. Hardware divider. Binary compatibility with the ARM9, ARM11, Cortex-R4 and Cortex-R5 embedded processors
Instruction Set	ARMv7-R architecture with Thumb®-2 and Thumb. DSP extensions. Optional floating point unit.
Cache controllers	Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes configurable from 4 to 64 KB. Cache lines are write-through
Tightly-Coupled Memories	Optional Tightly-Coupled Memory interfaces. TCMs are used for highly deterministic or low-latency applications that may not respond well to caching, e.g. instruction code for interrupt service routines and data that requires intense processing. Instruction and/or data TCMs. TCM size can be up to 128 KB.
Interrupt interface	Standard interrupt, IRQ, and non-maskable fast interrupt, FIQ, inputs are provided together with a fully intergrated Generic Interrupt Controller (GIC) supporting complex priority-based interrupt handling. The processor includes low-latency interrupt technology which allows long multi-cycle instructions to interrupted and restarted. Lengthy memory accesses are also deferred in certain circumstances. Worst case interrupt response can be as low as 20-cycles.
Memory Protection Unit	Optional MPU configures attributes for sixteen regions, each with resolution down to 32 Bytes. Regions can overlap, and the highest numbered region has highest priority.
Floating Point Unit	Optional Floating Point Unit (FPU) implements the ARM Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE754. Two FPU options are supported, either a single precision-only or both single and double precision. The FPU performance is optimized for both single and double precision calculations. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
ECC	Optional single-bit error correction and two-bit error detection for cache and/or TCM memories with ECC bits. Single-bit soft errors are automatically corrected by the processor. In addition full and flexible support for managing hard errors.
Master AMBA AXI bus	64-bit AMBA® AXI™ bus master for Level-2 memory and peripheral access.
Low latency memory port	A 64-bit AXI master port designed specifcally to connect to local memory. This local memory provides many of the benefits of TCM and in addition can be slower and lower power and also easily shared between coherent peripherals and the one or two Cortex-R7 processor cores.
Low Latency Peripheral Port (LLPP)	A dedicated 32-bit AXI port to integrate latency-sensitive peripherals more tightly with the processor.
Accelerator Coherency Port (ACP)	A 64-bit AXI slave port to enable for coherency between the processor(s) and external intelligent peripherals such as DMA controllers, Ethernet or Flexray interfaces.
Slave AXI bus	Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the TCMs for high speed streaming of data in and out of the processor.
Debug	Debug Access Port is provided. Its functionality can be extended using CoreSight SoC-400.
Trace	An interface suitable for connection to CoreSight Embedded Trace Module is present.
Dual core lock step support	A redundant Cortex-R7 CPU in lock-step is supported for fault tolerant/fault detecting dependable systems. Configuration Synthesizable Verilog RTL with facility to configure options for synthesis.

ARM System IP, Development Tools and Physical IP are used to implement complete Cortex-R7 systems.

CoreLink and CoreSight System IP

NIC-301	Configurable hierarchic low latency interconnect for AMBA 3 AXI, AHB-Lite and APB components. Configurations can range from a single bridge component, such as an AHB to AXI protocol bridge, to a large infrastructure of 128 masters and 64 slaves in combinations of different AMBA protocols.
QOS-301	Added to NIC-301 to minimize average latency and guarantee worst-case latency and bandwidth of critical interfaces such as DDR memory.
DMC-34x	Dynamic memory controllers providing highly efficient interfaces to DRAM by leveraging AXI interconnect features to optimize memory request scheduling and using built-in Quality of Service controls to manage the initiator’s latency and bandwidth requirements. Memory types supported include SDR, DDR, LPDDR (Mobile DDR), eDRAM, DDR2 and LPDDR2 (Mobile DDR2).
SMC-35x	Static memory controllers interface AXI interconnects to a range of non-volatile memories with highly configurable parameters. Memory types supported include SRAM, NAND Flash and NOR Flash.
L2C-310	Level-2 cache controller designed to boost performance while reducing overall traffic to system memory and therefore SoC energy consumption. Reducing demands on off-chip memory bandwidth frees up resources for other masters.
DMA-330	A highly flexible micro-programmable Direct Memory Access controller for high-end high-performance energy-efficient AXI-based processing systems.
PL192	An AMBA AHB advanced Vectored Interrupt Controller (VIC) supporting up to 32 vectored interrupts with programmable priority level and masking.
GIC390	An AMBA AHB and AXI scalable, configurable, low gate count Interrupt Controller which stores vector addresses in memory. Options include multi-processor and TrustZone support.
ETM-R7	The Embedded Trace Macrocell provides real-time instruction and data trace and is configured to capture information before and after a specified sequence of events with the processor at full speed.
CoreSight SoC-400	A comprehensive debug & trace design tool consisting of the CoreSight SoC components (Debug Access Port, Cross-Trigger logic, Trace Interfaces etc.) together with a design and verification environment for fast and powerful system design and implementation.

Development Tools

All Cortex-R processors are fully supported in the ARM Development Suite 5 (DS-5™) tool suite, as well as a wide range of third party tools, operating systems and EDA flows. ARM DS-5 software development tools are unique in their ability to provide solutions that take full advantage of the complete ARM technology portfolio. Tools specific to Cortex-R7 are:

ARM DS-5	ARM Compiler 5.0 with Thumb-2 optimized for Cortex-R7.
RTX Real-Time Kernel (Keil)	Royalty-free, deterministic RTOS with source code for high-speed real-time operation with low interrupt latency and flexible Scheduling. Small footprint for resource constrained systems, multithreading and thread-safe operation, kernel aware debug support in MDK-ARM.

Physical IP

ARM optimized Physical IP platforms for best-in-class implementations of Cortex-R7 on leading semiconductor process technologies.

Standard cell logic libraries	Available in a variety of different architectures, ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area.
Memory compilers and registers	A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.
Interface IP	A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces are optimized to deliver high data throughput performance with low pin counts.