Cortex-R5 Processor

Cortex-R5 Processor Image (View Larger Cortex-R5 Processor Image)

The ARM® Cortex®-R5 processor provides a high-performance solution for real-time applications and forms a simple migration path from the Cortex-R4 processor, and onwards to the higher performance Cortex-R7 processor.

The Cortex-R5 processor extends the feature set of the Cortex-R4 processor to enable higher levels of system performance, increased efficiency and reliability, and enhanced error management in dependable real-time systems. These system-level features include a high priority Low-Latency Peripheral Port (LLPP) for fast peripheral reads and writes, and an Accelerator Coherency Port (ACP) for greater efficiency and more reliable cache coherency with an external data source. A Safety Documentation Package is also available for the Cortex-R5 processor.

It is used in real-time applications in markets including mobile baseband, automotive, mass storage, industrial and medical.


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Like the Cortex-R4 processor, the Cortex-R5 processor is designed for implementation on advanced silicon processes with an emphasis on improved energy efficiency, real-time responsiveness, advanced features and ease of system design. The processor provides a highly flexible and efficient two-cycle local memory interface, enabling SoC designers to minimize system cost and energy consumption.

The Cortex-R5 processor integrates a number of advanced system level features beyond those of the Cortex-R4 to aid software development and improve reliability in safety and enterprise systems. These include the Low-Latency Peripheral Port (LLPP), an enhanced memory protection unit, a coherency interface to keep the Cortex-R5 caches fully synchronized with data being transferred by intelligent peripherals and enhanced ECC support that extends to all of the processor interfaces.

There are also dual-core configurations available for the Cortex-R5 processor. This can enable twice the performance with the ACP and Micro Snoop Control Unit (µSCU) maintaining data cache coherency with DMA I/O for both cores, and with each core having a LLPP for deterministic I/O control. Alternatively in the lock-step configuration, the second core provides redundancy for safety critical applications.

In addition, a Safety Documentation Package is available to speed time to market, simplify the certification effort for standards such as ISO 26262 and IEC 61508, and enable higher levels of certification to be obtained. To find out more about functional safety for the Cortex-R5 processor, please refer to the ARM Whitepaper on “Safety standards in the ARM ecosystem”.


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