.jpg)
Cortex-R4
The Cortex-R4 processor, designed for implementation on advanced silicon processes with an emphasis on improved energy efficiency, real-time responsiveness, advanced features and ease of system design. The processor provides a highly flexible and efficient two-cycle local memory interface, enabling SoC designers to minimize system cost and energy consumption.
Summary of Cortex-R4 Key Features
- Fast – high performance 1.66 DMIPS/MHz
- Power-efficient, 8-stage dual issue pipeline with instruction pre-fetch and branch prediction
- ARMv7R architecture - Thumb-2 / ARM instructions
- Hardware divide, SIMD, DSP, SP/DP FPU option
- Harvard I + D caches, 64-bit AMBA AXI-3
- Deterministic – fast interrupt response
- Vectored Interrupt Controller port
- Low Latency Interrupt Mode (LLIM) to accelerate interrupt entry whenever possible without waiting for the current instruction or memory access to complete
- Tightly-Coupled Memory system which provides a second level-1 memory besides the cache for storing critical code and data such as interrupt service routines which can then be immediately executed without waiting for cache evictions and fetches from main memory
- Low Latency Peripheral Port (LLPP) which provides for peripheral device access with a guaranteed low latency
- Reliable – error handling built into core
- Memory Protection Unit
- ECC and Parity protection on L1 memories
- Dual core lock-step configuration
- Cost-effective and low cost of ownership
- Synthesis configurable for optimum PPA
- CoreSight debug and trace
)
