Cortex-M0+ Processor

*  http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1505&suite=CORE  

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone

*** Base usable configuration includes 1 IRQ + NMI, excludes debug

ARM Cortex-M technologies

Each Cortex-M series processor delivers specific benefits, underpinned by fundamental technologies that make Cortex-M processors ideal for a broad range of embedded applications.

CMSIS

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series.The CMSIS enables consistent and simple software interfaces to the processor for interface peripherals, real-time operating systems, and middleware, simplifying software re-use. With a reduced learning curve for new microcontroller developers, CMSIS shortens the time to market for new products.

In-depth: Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of all Cortex-M processors and provides the processors' outstanding interrupt handling abilities. In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors, the NVIC support up to 32 interrupts (IRQ), a Non-Maskable Interrupt (NMI) and various system exceptions. The Cortex-M3 and Cortex-M4 processors extend the VIC to support up to 240 IRQs, 1 NMI and further system exceptions.

Most of the NVIC settings are programmable. The configuration registers are part of the memory map and can be accessed as C pointers. The CMSIS library also provided various helper functions to make interrupt control easier.
Inside the NVIC, each interrupt source is assigned an interrupt priority. A few of the system exceptions like such as NMI haves a fixed priority level, and others hashave programmable priority levels. By assigning different priorities to each interrupt, the NVIC can support Nested Interrupts automatically without any software intervention.

The architecture provides 8-bits of priority level settings for each programmable interrupt or exception. To reduce gate count, only parts of these registers are implemented. In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture), 4 programmable levels are provided. In the Cortex-M3 and Cortex-M4 processors (ARMv7-M architecture), the designs allow from 8 priority levels to 256 levels.

To make the Cortex-M processors easier to use, the Cortex-M processor uses a stack based exception model. When an exception takes place a number of registers are pushed on to the stack. These registers are restored to their original values when the exception handler completes. This allows the exception handlers to be written as normal C functions, and also reduce the hidden software overhead ofin interrupt processing.

In addition, the Cortex-M processors use a vector table that contains the address of the function to be executed for eacha particular interrupt handler. On accepting an interrupt, the processor fetches the address from the vector table. Again, this avoids software overhead and reduces interrupt latency.

Various optimization techniques are also used in the Cortex-M processor implementationss to make interrupt processing more efficiency and make the system more responsive:

Tail chaining – If another exception is pending when an ISR exits, the processor does not restore all saved registers from the stack and instead moves on to the next ISR. This reduces the latency when switching from one exception handler to another.

Stack pop pre-emption – If another exception occurs during the unstacking process of an exception, the processor abandons the stack Pop and services the new interrupt immediately as shown above. By pre-empting and switching to the second interrupt without completing the state restore and save, the NVIC achieves lower latency in a deterministic manner.

Late arrival – If a higher priority interrupt arrives during the stacking of a lower priority interrupt, the processor fetches a new vector address and processes the higher priority interrupt first.

With these optimizations, the interrupt overhead reduces as the interrupt loading increases, allowing high interrupt processing throughput in embedded systems.

ARM Cortex-M code size advantage explained

ARM Cortex-M processors offer superior code density to 8-bit and 16-bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory. In this section we examine the reasons for this advantage.

Instruction width

It is a common misconception that 8-bit microcontrollers use 8-bit instructions and ARM Cortex-M processor-based microcontrollers use 32-bit instructions. In reality for example, the PIC18 and PIC16 instruction sizes are 16-bit and 14-bit respectively. For the 8051 architecture, although some instructions are 1 byte long, many others are 2 or 3 bytes long. The same also applies to 16-bit architectures, where some instructions can take 6 bytes or more of memory.

The ARM Cortex-M3 and Cortex-M0 processors utilize the ARM Thumb^®-2 technology which provides excellent code density. With Thumb-2 technology, the Cortex-M processors support a fundamental base of 16-bit Thumb instructions, extended to include more powerful 32-bit instructions. In many cases a C compiler will use the 16-bit version of the instruction unless the operation can be carried out more efficiently using a 32-bit version.

Instruction efficiency

This picture is not complete without also considering that ARM Cortex-M processor instructions are more powerful. There are many circumstances where a single Thumb instruction equates to several 8/16-bit microcontroller instructions; this means that Cortex-M devices have smaller code and achieve the same task at lower bus speed.

Comparing 16-bit multiply operations across processor architectures

N.B. The Cortex-M multiply in fact performs a 32-bit multiply, here we assume r0 and r1 contain 16-bit data.

Compact data footprint

It is important to note that Cortex-M processors have support for 8-bit and 16-bit data tranfers, making efficient use of data memory. This means programmers can continue to use the same data-types as they have in 8/16-bit targeted software.

Energy efficiency advantage

The demand for ever lower-cost products with increasing connectivity (e.g. USB, Bluetooth, IEEE 802.15) and sophisticated analog sensors (e.g. accelerometers, touch screens) has resulted in the need to more tightly integrate analog devices with digital functionality to pre-process and communicate data. Most 8-bit devices do not offer the performance to sustain these tasks without significant increases in MHz and therefore power, and so embedded developers are required to look for alternative devices with more advanced processor technology. The 16-bit devices have previously been used to address energy efficiency concerns in microcontroller applications. However, the relative performance inefficiencies of 16-bit devices mean they will generally require a longer active duty cycle or higher clock frequency to accomplish the same task as a 32-bit device.

Ease of software development

Software development for ARM Cortex processor-based microcontrollers can be much easier than for 8-bit microcontroller products. Not only is the Cortex processor fully C programmable, it also comes with various enhanced debug features to help locating problems in software. There are also plenty of examples and tutorials on the internet, including many from ARM processor-based MCU vendor's websites, alongside any additional resources included in MCU development kits.

Resources

In this section, you will find useful documentation, white papers and tutorials on ARM Cortex-M processors and related technologies.

For further information including information on development tools, software, boards, and a device database, CMSIS and mBed visit the ARM Embedded Microsite

Books

Definitive Guide to the ARM Cortex-M0 A comprehensive guide to programming and implementing the groundbreaking ARM Cortex-M0 processor

Definitive Guide to the ARM Cortex-M3 A comprehensive guide to programming and implementing the groundbreaking ARM Cortex-M3 processor

 

Documentation for Cortex-M device users

• Cortex-M0+ Introduction (200KB PDF)
• Cortex-M1 FPGA Development Kit Tutorial
• Migrating from ARM7 to Cortex-M3 (256 KB )

Software development tools for Cortex-M device users

• Keil
• mbed
• Third party tools and RTOS support

Find Cortex-M based microcontrollers

• Keil microcontroller device database
• ARM MCU Community - www.onarm.com
• Find an ARM Partner

Universities

• ARM University Program

Related User Guides and App Notes

• Cortex-M0/3/4 Devices Generic User Guides
  • Developer Guides and Articles
    • Software Development
      • Cortex-M0 Devices Generic User Guide
      • Cortex-M3 Devices Generic User Guide
      • Cortex-M4 Devices Generic User Guide
• Instruction Timing Information
  • Cortex-M0 Technical Reference Manual (TRM)
  • Cortex-M3 Technical Reference Manual (TRM)
  • Cortex-M4 Technical Reference Manual (TRM)
• Architecture (requires registration)
  • ARMv7-M Architecture Reference Manual
  • ARMv6-M Architecture Reference Manual
• ARM Application Notes
  • AN237 - Migrating from 8051 to Cortex Microcontrollers
  • AN234 - Migrating from PIC Microcontrollers to Cortex-M3
  • AN179 - Cortex™-M3 Embedded Software Development
• Keil Application Notes
  • 193: Migrating to MDK-ARM from RVDS
  • 197: Serial-Wire Debug and Realtime Trace on STM32 Devices
  • 202: MDK-ARM Compiler Optimizations
  • 208: Keil uVision and Actel SmartFusion
  • 209: Using Cortex-M3 and Cortex-M4 Fault Exceptions
  • 220: Memory Configuration on Freescale Kinetis devices
  • 221: Using CMSIS-DSP Algorithms with RTX

DesignStart for Processor IP

• Cortex-M3 DesignStart Processor
• Cortex-M0 DesignStart Processor