Cortex-M0 Processor

ARM Cortex-M0 Features

 
* The ARM Cortex-M0 processor implements the Thumb instruction set, including a small number of 32-bit instructions that use Thumb-2 technology. This is a binary upwards compatible subset of the instruction sets supported by ARM Cortex-M3 and ARM Cortex-M4.

ARM Cortex-M technologies

Each Cortex-M series processor delivers specific benefits, but all are underpinned by fundamental technologies than make Cortex-M processors ideal for a broad range of embedded applications.

CMSIS

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series.  The CMSIS enables consistent and simple software interfaces to the processor for interface peripherals, real-time operating systems, and middleware, simplifying software re-use. With CMSIS the learning curve for new microcontroller developers is reduced, shortening time to market for new products.

In-depth: Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of Cortex-M processors and provides the processors' outstanding interrupt handling abilities.

The Cortex-M processor uses a vector table that contains the address of the function to be executed for a particular interrupt handler. On accepting an interrupt, the processor fetches the address from the vector table.

To reduce gate count and enhance system flexibility, the Cortex-M processor uses a stack based exception model. When an exception takes place critical general purpose registers are pushed on to the stack. Once the stacking and instruction fetch are completed, the interrupt service routine or fault handler is executed, followed by the automatic restoration of the registers to enable the interrupted program to resume normal execution. This approach removes the need to write assembler wrappers that are required to perform stack manipulation for traditional C-based interrupt service routines, making application development significantly easier. The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by exerting higher priority.

Complete response to interrupts in hardware

The interrupt response of Cortex-M series processor is the number of cycles from interrupt signal to execution of interrupt service routine. It includes: 

• Detecting the interrupt
• Optimal handling of back-to-back or late arriving interrupts (see below)
• Fetching the vector address
• Stacking corruptible registers
• Branching to the interrupt handler

These are tasks that are performed in hardware and included in the interrupt response cycle time quoted for Cortex-M processors. In many other architectures these tasks must be performed in a software in the interrupt handler, introducing latency and complexity.

Tail chaining in the NVIC

In the case of back-to-back interrupts, traditional systems would repeat the complete state save and restore cycle twice, resulting in higher latency. The Cortex-M processors simplify moving between active and pending interrupts by implementing tail-chaining technology in the NVIC hardware. The processor state is automatically saved on interrupt entry, and restored on interrupt exit, in fewer cycles than a software implementation, significantly enhancing performance in low MHz systems.

Response of the NVIC to late arrival of higher priority interrupts

In case of the late arrival of a higher priority interrupt during the execution of the stack Push for a previous interrupt, the NVIC immediately fetches a new vector address to service the pending interrupt, as shown above. The Cortex-M NVIC provides deterministic response to these possibilities with support for late arrival and pre-emption.

Stack pop pre-emption by the NVIC

Similarly, the NVIC abandons a stack Pop if an exception arrives and services the new interrupt immediately as shown above. By pre-empting and switching to the second interrupt without completing the state restore and save, the NVIC achieves lower latency in a deterministic manner.

Moving from 8/16-bit to ARM Cortex-M

ARM Cortex-M code size advantage explained

ARM Cortex-M processors offer superior code density to 8-bit and 16-bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory. In this section we examine the reasons for this advantage.

Code size comparison using relative EEMBC CoreMark test size.

Instruction width

It is a common misconception that 8-bit microcontrollers use 8-bit instructions and ARM Cortex-M processor-based microcontrollers use 32-bit instructions. In reality, the PIC18 and PIC16 instruction sizes are 16-bit and 14-bit respectively. For the 8051 architecture, although some instructions are 1 byte long, many others are 2 or 3 bytes long.  The same generally applies to 16-bit architectures, where some instructions can take 6 bytes or more of memory.

The ARM Cortex-M3 and Cortex-M0 processors utilize the ARM Thumb^®-2 technology which provides excellent code density. With Thumb-2 technology, the Cortex-M processors support a fundamental base of 16-bit Thumb instructions, extended to include more powerful 32-bit instructions. In many cases a C compiler will use the 16-bit version of the instruction unless the operation can be carried out more efficiently using a 32-bit version.

Instruction efficiency

This picture is not complete without also considering that ARM Cortex-M processor instructions are more powerful. There are many circumstances where a single Thumb instruction equates to several 8/16-bit microcontroller instructions; this means that Cortex-M devices have smaller code and achieve the same task at lower bus speed.

 N.B. The Cortex-M multiply in fact performs a 32-bit multiply, here we assume r0 and r1 contain 16-bit data.

Compact data footprint

It is important to note that Cortex-M processors have support for 8-bit and 16-bit data tranfers, making efficient use of data memory. This means programmers can continue to use the same data-types as they have in 8/16-bit targeted software.

Energy efficiency advantage

The demand for ever lower-cost products with increasing connectivity (e.g. USB, Bluetooth, IEEE 802.15) and sophisticated analog sensors (e.g. accelerometers, touch screens) has resulted in the need to more tightly integrate analog devices with digital functionality to pre-process and communicate data. Most 8-bit devices do not offer the performance to sustain these tasks without significant increases in MHz and therefore power, and so embedded developers are required to look for alternative devices with more advanced processor technology. The 16-bit devices have previously been used to address energy efficiency concerns in microcontroller applications. However, the relative performance inefficiencies of 16-bit devices mean they will generally require a longer active duty cycle or higher clock frequency to accomplish the same task as a 32-bit device.

Ease of software development

Software development for ARM Cortex processor-based microcontrollers can be much easier than for 8-bit microcontroller products.  Not only is the Cortex processor fully C programmable, it also comes with various enhanced debug features to help locating problems in software.  There are also plenty of examples and tutorials on the internet, including many from ARM processor-based MCU vendor’s websites, alongside any additional resources included in MCU development kits.

Resources

In this section you will find useful documentation, white papers and tutorials on ARM Cortex-M processors and related technologies.

Documentation for Cortex-M device users

• Cortex-M1 FPGA Development Kit Tutorial
• Migrating from ARM7 to Cortex-M3 (256 KB )

Software development tools for Cortex-M device users

• Keil
• mbed
• Third party tools and RTOS support

Find Cortex-M based microcontrollers

• Keil microcontroller device database
• ARM MCU Community - www.onarm.com
• Find an ARM Partner

Universities

• ARM University Program