Cortex-A7 Processor

Cortex-A7 Processor Image (View Larger Cortex-A7 Processor Image)
The ARM® Cortex®-A7 MPCore™ processor is the most power-efficient application processor ARM has ever developed, and dramatically extends ARM’s low-power leadership in entry-level smartphones, tablets, high-end wearables and other advanced mobile devices. The Cortex-A7 led the multicore revolution for entry-level and mid-range mobile smartphones, and devices based on the popular quad- and octa- core configurations are shipping in huge volumes.

The architecture and feature set of the Cortex-A7 are identical to the Cortex-A15 and Cortex-A17 processors, with differences in the Cortex-A7 processor's microarchitecture focused on providing optimum energy efficiency. This enables the Cortex-A7 to be paired with either of these processors in a big.LITTLE configuration to provide the ultimate combination of high-performance with ultra-low power consumption.

As a stand-alone processor, the Cortex-A7 powers sub-$100 entry-level smartphones today, which perform better than $500 high-end smartphones in 2012.



The Cortex-A7 processor is a very energy-efficient applications processor designed to provide rich performance in entry level and mid-range smartphones, today's high-end wearables and other low-power embedded and consumer applications.

The processor is fully compatible with other ARMv7 Cortex-A series processors and incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including virtualization support in hardware, Large Physical Address Extensions (LPAE), NEON, and AMBA 4 bus interface.

The Cortex-A7 processor:

  • Provides best power-efficiency and low footprint as a stand-alone applications processor
    • Similar performance to mainstream smartphone in 2012 based on Cortex-A9
    • Up to 20% more single thread performance compared to Cortex-A5 at similar energy efficiency 
  • Is used as an energy-efficient LITTLE CPU with a high-performance Cortex-A15 or Cortex A-17 processor to enable ARM big.LITTLE Processing
    • Software can run seamlessly on an energy-efficient Cortex-A7 processor and on a high-performance Cortex-A15 or Cortex-A17 processor as needed without recompilation
    • The LITTLE Cortex-A7 processor powers low processing intensity tasks such as scrolling or reading a web page, and lighter weight tasks like texting, e-mail and audio, while the big processor manages periods of high processing intensity tasks, such as initial web page rendering and game physics calculation. This reduces energy consumption and improves processing performance.
    • AMBA 4 ACE coherency interface enables sub-20us context migration between big and LITTLE CPU clusters


The Cortex-A7 processor has been licensed by a large number of the industry's leading silicon manufacturers including:

Performance improvements in Cortex-A7 processor

The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It is feature compatible with the high-performance Cortex-A15 processor and supports 40bit physical memory addressing and hardware virtualization support. The key microarchitecture improvements in Cortex-A7 are listed below:

  • Integrated L2 cache
    • Lower transaction latencies
    • Improved OS support for L2 cache maintenance due to simplified software control
    • Designed with a low power approach
      • Consecutive tag-data lookup and fixed 8 way-set associativity balances performance against lookup energy
      • External request on L2 miss – non-speculative to reduce energy
  • Branch prediction improvements
    • BTIC caches fetches after a direct branch, hides branch shadow on tight loops
  • Improved memory system performance
    • 64-bit Load Store path, improves integer and NEON performance over Cortex-A5 (32b path)
    • 128-bit AMBA 4 buses improves bandwidth 
    • Increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5)
      • Increases performance for large workloads like web browsing 

Power, Performance and Area (PPA) for Cortex-A7

Floorplan snapshot for Cortex-A7 CPU

 PPA in 28nm


Cortex-A7 single core layout image

  • Performance  (silicon frequency)
    • 1.2 - 1.6 GHz at 28nm
  • Area
    • 0.45mm2 (1 core) 
      • With FPU & NEON™,
      • 32K L1 instruction and data cache size  
  •  Total Power
    • Less than 100mW for typical conditions



Cortex-A7 processor delivers similar performance as a Cortex-A9 based high-end device


Cortex-A7 MPCore
Architecture ARMv7-A
  • 1-4X SMP within a single processor cluster
  • Multiple coherent SMP processor clusters through AMBA® 4 technology
ISA Support
  • ARMv7-A
  • Thumb-2
  • TrustZone® security technology
  • NEON™ Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
Memory Management ARMv7 Memory Management Unit
Debug and Trace CoreSight™ SoC-400

Cortex-A7 MPCore Key Features
Thumb-2 Technology Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions
TrustZone Technology Ensures reliable implementation of security applications ranging from digital rights management to electronic payment
NEON NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis
Floating point operations Hardware support for floating-point operations in half-, single- and double-precision floating point arithmetic. The floating-point capabilities of the Cortex-A7 processor offer increased performance for floating point arithmetic used in next generation of consumer products such as Internet appliances, set-top boxes, and home gateways.
Hardware Virtualization Highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to access simultaneously the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.
Large Physical Address Extensions (LPAE) The introduction of Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.
Optimized Level 1 Caches Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Caches are configurable size 8kB~64KB for instruction and for data. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software development
Integrated, Configurable Size Level 2 Cache Controller Providing low latency and high bandwidth access to up to 1 MB of cached memory in high frequency designs, or design needing to reduce the power consumption associated with off chip memory access. The L2 cache is optional on Cortex-A7.
AMBA® 4 Cache Coherent Interconnect (CCI) The CCI provides AMBA 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A7 MPCore processors, better utilizing caches and simplifying software development. This feature is essential for high bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink™ network interconnect and memory controller IP, the CCI increases system performance and power efficiency.
Cortex-A7 NEON Media Processing Engine (MPE) The Cortex-A7 MPE provides an engine that offers both the performance and functionality of the Cortex-A7 Floating-Point Unit and an implementation of the NEON Advanced SIMD instruction set for further acceleration of media and signal processing functions. The MPE extends the Cortex-A7 processor's floating-point unit (FPU) to provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of SIMD operations over 8, 16 and 32-bit integer and 32-bit Floating-Point data quantities.
Cortex-A7 Floating-Point Unit (FPU) The FPU provides high-performance single, and double precision Floating-Point instructions compatible with the ARM VFPv4 architecture that is software compatible with previous generations of ARM Floating-Point coprocessor.

Advanced MultiCore Features
The processor also utilizes the widely established ARM MPCore multicore technology, enabling performance scalability and control over power consumption to exceed the performance of today's comparable high-performance devices while remaining within tight mobile power constraints. Multicore processing provides the ability for any of the four component processors to be shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is utilized to meet the demand while still sharing the workload to keep power consumption as low as possible.
Snoop Control Unit (SCU)
  • The SCU is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other capabilities for the processor.
  • The Cortex-A7 MPCore processor also exposes these capabilities to other system accelerators and non-cached DMA driven peripherals to increase performance and reduce system wide power consumption.
  • This system coherence also reduces software complexity involved maintaining software coherence within each OS driver.
AMBA® 4 AMBA Coherency Extension (ACE)-Lite
  • This mechanism enables external non-cached bus masters to perform coherent reads and writes to the Cortex-A7 memory map.
  • The snoop control unit manages coherency and makes connection through AMBA-4 ACE-Lite; this acts as a functional replacement for the accelerator coherency port (ACP) that was present in Cortex-A5 and Cortex-A9. ACE-Lite is particularly useful for applications where the Cortex-A7 CPU is managing IO traffic driven by an external DMA.
Generic Interrupt Controller
  • Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts.
  • Supporting up to 480 independent interrupts, under software control, each interrupt can be distributed across CPU, hardware prioritized, and routed between the operating system and TrustZone software management layer.
  • This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor

Cortex-A7 MP in an entry level smartphone platform

Cortex-A7 used in a high end mobile platform using big.LITTLE technology

The Cortex-A7 MPCore processor incorporates, and benefits from support by a broad range of ARM technology including System IP, Physical IP, and development tools. A broad range of SoC and software design solutions, tools and services from the ARM® Connected Community complements this technology. This provides ARM Partners with a smooth path through the development, verification and production of fully functioning, compelling devices while significantly reducing the time-to-market.

System IP

The ARM CoreLink™ interconnect and memory controller IP addresses the critical challenge of efficiently moving and storing data between multiple Cortex-A7 MPCore processors, high-performance media processors and dynamic memories to optimize the system performance and power consumption of the SoC. The CoreLink system IP enables SoC designers to maximize the utilization of system memory bandwidth and reduce static and dynamic latencies. On top of this, the ARM CoreSight™ technology provides complete on-chip debug and correlated, real-time trace visibility for all cores of the Cortex-A7 MPCore processor, reducing risk and speeding development of high quality multiprocessing software. The new AMBA® 4 Cache Coherent Interconnect (CCI) provides optimum system bandwidth and latency. The CCI provides AMBA 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A7 MPCore processors, better utilizing caches and simplifying software development. This feature is essential for high bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink network interconnect and memory controller IP, the CCI increases system performance and power efficiency.

Physical IP

ARM Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A7 processor at 40nm and below. A set of high performance Processor Optimization Packs (POPs) containing advanced ARM Physical IP for 28nm technologies to enable rapid development of leadership physical implementation supports the Cortex-A7 processor. ARM is also leading the way to 20nm optimizations. Optimization packs support ARM's strategy of offering specifically targeted Physical IP to enable Partners to achieve tuned implementations of ARM cores. ARM is uniquely able to design the optimization packs in parallel with the Cortex-A7 MPCore processor architecture, enabling the processor and physical IP combination to deliver workstation class performance in a mobile power envelope while facilitating rapid time-to-market.

Development Tools for Cortex-A7

Cortex-A7 processors are fully supported by ARM DS-5 Development Studio as well as a wide range of third party tools, operating systems and EDA flows. DS-5 represents a comprehensive range of software tools to create, debug and optimize systems based on the Cortex-A7 MPCore processor.

It incorporates DS-5 Debugger, whose powerful and intuitive graphical environment enables fast debugging of bare-metal, Linux and Android native applications. DS-5 Debugger provides pre-defined configurations for Fixed Virtual Platforms including Cortex-A15/Cortex-A7 big.LITTLE, and ARM Versatile Express boards, enabling early software development before silicon availability.

In addition, Streamline performance analyzer simplifies the identification of hot spots in software and load balancing between cores and clusters with a brilliantly intuitive graphical display.

ARM Compiler 5 includes specific optimizations for the Cortex-A7 MPCore processor, enabling code generation from the earliest stages of your project and is included in DS-5.

Graphics Processors

The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.


ARM training courses and Active Assist on-site system-design advisory services enable licensees to integrate efficiently the Cortex-A7 MPCore processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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