Cortex-A5 Processor

     Area with 16K/16K cache

     Area with 16K/16K cache + NEON    

 1-4 cores

Single core version also available

• ARM
• Thumb®-2 / Thumb
• DSP & SIMD extensions
• VFPv3 Floating Point (optional)
• NEON™ Advanced SIMD (optional)
• Jazelle® DBX and RCT

Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions.  

Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry Partners.

The optional Cortex-A5 NEON MPE provides both the performance and functionality of the Cortex-A5 Floating Point Unit plus an implementation of the ARM NEON Advanced SIMD instruction set for further acceleration of media and signal processing functions.

The MPE extends the Cortex-A5 Floating Point Unit (FPU) an additional register set supporting a rich set of SIMD operations over  8, 16, and 32-bit integer and 32-bit Floating-Point data types.

The optional Cortex-A5 FPU is an implementation of the ARM Vector Floating Point v3 architecture, with 16 double-precision registers (VFPv3-D16). The unit provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754).

The FPU supports all data-processing instructions and data types in the VFPv3 architecture and fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.

Provides up to 3x reduction on code size for Just-in-time (JIT) and ahead-of-time compilation of bytecode languages while also supporting direct byte code execution of Java instructions for acceleration in traditional virtual machines

The power optimized L1 Instruction and Data Caches are individually configurable from 4-64K.  Optimized instances of ARM SRAMs are available.

The Cortex-A5 implements a 64-bit unified AXI bus that supports multiple outstanding transactions, and has over 3x the memory bandwidth of the ARM1176JZ-S.

 Advanced Multicore Technologies

The SCU is the central intelligence in the ARM multicore technology and is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other capabilities for all multicore technology enabled processors.

The Cortex-A5 MPCore processor also exposes these capabilities to other system accelerators and non-cached DMA driven mastering peripherals so as to increase the performance and reduce the system wide power consumption by sharing access to the processor’s cache hierarchy. This system coherence also reduces the software complexity involved in otherwise maintaining software coherence within each OS driver.

This AMBA® 3 AXI™ compatible slave interface on the SCU provides an interconnect point for a range of system masters that - for overall system performance, power consumption or reasons of software simplification - are better interfaced directly with the Cortex-A5 MPCore processor.

The interface acts as a standard AMBA 3 AXI slave, and supports all standard read and write transactions without any additional coherence requirements placed on attached components. However, any read transactions to a coherent region of memory will interact with the SCU to test whether the required information is already stored within the processor L1 caches. If it is, it is returned directly to the requesting component. If it missed in the L1 cache, then there is also the opportunity to hit in L2 cache before finally being forwarded to the main memory.

For write transactions to any coherent memory region, the SCU will enforce coherence before the write is forwarded to the memory system. The transaction may also optionally allocate into the L2 cache hence removing the power and performance impact of writing directly through to the off chip memory

Implementing the recently standardized and architected ARM interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritisation of system interrupts. Supporting up to 224 independent interrupts under software control, each interrupt can be distributed across CPU, hardware prioritised, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a paravirtualization manager.

AXI

AXI

DMA-330 , PL330

AXI

L2C-310 , PL310

AXI

DMC-340 , PL340

AXI

DMC-342

AXI

AXI

PL380

ATB

CDK-11

Mali-55GPU