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ARM926 Processor

ARM926 Processor Image
The ARM926EJ-S™ processor features a Jazelle® technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces and memory management unit (MMU). It also provides separate instruction and data AMBA® AHB™ interfaces suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set which includes an enhanced 16 x 32-bit multiplier capable of single cycle MAC operations and 16-bit fixed point DSP instructions to enhance performance of many signal processing applications as well as supporting Thumb® technology.

A hard macro implementation of the ARM926EJ processor is available from the ARM Processor Foundry Program and from the DesignStart Program.

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Overview

A powerful application processor for platform OS based applications

The ARM926EJ-S processor is the entry point processor capable of supporting a full Operating System such as Linux, Windows CE, and Symbian. An ideal choice for many applications, the ARM926EJ-S processor is one of the most popular ARM processors.

Some of the features offered by the ARM926EJ-S processor are:

  • Java acceleration
  • DSP extensions
  • Optional floating point unit
  • Flexible local memory system with cache and exceptional Tightly Coupled Memory (TCM) integration
  • Binary compatibility with the ARM7TDMI® processor

Industry standard

Over 5 Billion ARM9 processors have been shipped so far

The ARM926EJ-S processor has been licensed by over 100 silicon vendors worldwide, and continues to be successfully deployed across a wide range of products and applications.

By offering stable and proven performance, it provides designers a low risk solution, with very fast time to market.

Range of application

The ARM926EJ-S is used in a a wide range of advanced digital products:

Product Type Application

Consumer

 Smartphones, PDA, Set top box, PMP, Electronic toys, Digital still cameras, Digital video cameras etc

Networking

 Wireless LAN, 802.11, Bluetooth, Firewire, SCSI, 2.5G/3G Baseband etc

Automotive

 Power train, ABS, Body systems, Navigation, Infotainment etc

Embedded

 USB controllers,bluetooth controllers, medical scanners etc

Storage 

 HDD controllers, solid state drives etc

Platform OS support

The ARM926EJ-S processor features an MMU, allowing for the use of fully featured OS such as Linux, Windows CE, and Symbian.

Accelerated Java Performance

  • Jazelle® DBX is widely used to deliver very high performance Java in mobile handsets and other consumer devices without impacting memory consumption, battery life or user experience.
  • Jazelle RCT can be used to significantly reduce the code bloat associated with AOT and JIT compilation, making AOT technology viable on mass-market devices.
  • Additionally Jazelle RCT can also be used to support execution environments beyond Java, such as Microsoft .NET Compact Framework, Python and others.

Flexible

Customizable for feature-rich and cost-sensitive applications

  • Configurable Memory Management Unit
  • Highly configurable cache & TCM plus bus interface
  • Flexible debug and trace infrastructure
  • Optional Floating Point Unit (IEE754)

Rich ecosystem of OS, RTOS, and tools support

Over 650 members in the Connected Community supporting ARM926EJ-S processors

  • Broadest ecosystem of compilers, debuggers and RTOS tools in the industry
  • Plentiful design services partners to aid in design task
  • Large variety of third party IP available to integrate with processors

ARM926EJ-S Performance, Power & Area  
 Process

 TSMC 180nm G

TSMC 130nm G

TSMC 90nm G

 

 Speed Optimized

Speed Optimized 

Area Optimized 

Speed Optimized 

Area Optimized 
Standard Cell Library

 ARM SC9

ARM SC12 

ARM SC9 

ARM SC12 

ARM SC7 
Performance (Total DMIPS)

 220

 304

 262

 517

275
Performance (DMIPS/MHz)

1.1

1.1

1.1

1.1

1.1
Max Frequency* (MHz)

200

276

238

470

250
Cache Size

8K/8K

8K/8K

8K/8K

8K/8K

8K/8K
Area - with cache (mm2)

6.5

2.78

2.39

1.40

0.85
Area - w/o cache (mm2)

 3.0

 1.61 

 1.45

 1.01

 0.50 
Power with cache (mW/MHz)

-

-

0.48

0.235

0.14
Power w/o cache (mW/MHz)

-

-

0.36

0.20

0.11

Power Efficiency† - with cache (DMIPS/mW)

-

-

2.29

4.68

7.85
Power Efficiency† w/o cache (DMIPS/mw)

-

-

3.05

5.5

10.0

 

Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Physical IP standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

The area no cache numbers quoted exclude RAM area, but include all logic including memory management, cache control and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches and all necessary RAMs.

* Worst case conditions  –   0.18µm process - 1.62V, 125C, slow silicon ;  0.13µm process - 1.08V, 125C, slow silicon ;  90nm process - 0.9V, 125C, slow silicon

†  Typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ;  0.13µm process - 1.2V, 25C, typical silicon ; 90nm process - 1V, 25C, typical silicon

 


ARM926EJ-S
Architecture ARMv5TE
ISA Support
Pipeline 5 stage
Dhrystone Performance 1.1 DMIPS / MHz
Interrupts FIQ/IRQ
Memory System Main / TCM Interface
Bus 2x AMBA® AHB™ Interfaces
  • AHB-lite Master for regular use
  • AHB-lite slave for DMA TCM access
Debug & Trace
  • EmbeddedICE-RT real-time debug unit
  • JTAG interface unit
  • Interface for direct connection to Embedded Trace Macrocell (CoreSight™ ETM9)
Availability Synthesizable and hard macro

 

 

ARM926EJ-S Key Features
ARM and Thumb ISA The ARM 32-bit instruction set is used in applications requiring high performance. ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries. All ARM instructions can also be "conditionalized" to only execute when previous instructions have set a particular condition code.
Thumb is an extension to the 32-bit ARM architecture. The Thumb instruction set features a subset of the most commonly used 32-bit ARM instructions which have been compressed into 16-bit wide opcodes. On execution, these 16-bit instructions are decompressed transparently to full 32-bit ARM instructions in real time without performance loss.
Designers can use both 16-bit Thumb and 32-bit ARM instructions sets and therefore have the flexibility to emphasize performance or code size on a sub-routine level as their applications require.
Configurable Instruction and Data Caches The ARM926EJ-S processor includes an Instruction Cache (ICache) and a Data Cache (DCache). The size of the caches can be from 4KB to 128KB, in power of two increments.
Configurable Instruction and Data TCMs The ARM926EJ-S processor supports highly configurable instruction and data TCMs. TCMs are typically used for applications that may not respond well to caching, such as highly deterministic or low-latency applications with finite closed-loop control. TCM accesses are deterministic and do not access the AHB. Therefore, you can use the DTCM and ITCM to store real-time, performance-critical code.
The Instruction TCM typically handles interrupts or exceptions, and the Data TCM handles data intensive tasks, such as audio or video processing.
The ITCM and DTCM sizes can be independently configured as 0KB or 1KB-1MB in power-of-two increments
MMU The ARM926EJ-S processor features an ARM architecture v5 MMU. It provides virtual memory features required by systems operating on platforms such as Symbian OS, WindowsCE, and Linux.
A single set of two-level page tables stored in main memory controls address translation, permission checks, and memory region attributes for both data and instruction accesses.
The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables.
To support both sections and pages, there are two levels of address translation. The MMU puts the translated physical addresses into the MMU Translation Lookaside Buffer TLB.
Key MMU features are:
  • Standard ARM architecture v5 MMU mapping sizes, domains, and access protection scheme
  • Mapping sizes are 1MB (sections), 64KB (large pages), 4KB (small pages), and 1KB (tiny pages)
  • Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)
Jazelle Java acceleration The ARM926EJ-S processor includes features for efficient execution of byte codes, providing Java performance similar to JIT, but without the associated code overhead.
DSP Extensions The ARM9 family benefits from powerful DSP extensions that enable low-power, high-performance ARM9 based solutions for a broad range of software applications such as servo motor control, Voice over IP and video & audio codecs.
The ARM DSP extensions enable increased DSP performance without the need for very high clock frequencies. This performance is achieved with almost no increase in power consumption on a typical implementation. In many applications including smartphones and similar embedded systems requiring considerable signal processing, the DSP extensions can often eliminate the need for additional hardware accelerators.
  • Single-cycle 16x16 and 32x16 MAC implementations
  • 2-3 x DSP performance improvement over ARM7™-based CPU products
  • Zero overhead saturation extension support
  • Instructions to load and store pairs of registers, with enhanced addressing modes
  • CLZ instruction improves normalisation in arithmetic operations and improves divide performance

Compilers targeting the ARM architecture can use these DSP extensions to improve code-generation for standard C and C++ software, or allow software developers to explicitly request use of these extension via intrinsics or inline assembly code.
Optional VFP9-S  Floating Point Unit The VFP9-S coprocessor provides IEEE 754 standard-compatible operations. Designed specifically for the ARM9 processor family, the VFP9-S coprocessor provides full support of single-precision and double-precision add, subtract, multiply, divide, and multiply with accumulate operations. Conversions between floating-point data formats and ARM integer word format are provided, with special operations to perform the conversion in round-toward-zero mode for high-level language support.
The VFP9-S coprocessor provides a performance-power-area solution for embedded applications and high performance for general-purpose applications, such as Java.
The VFP9-S coprocessor is optimized for:
  • High data transfer bandwidth through 32-bit split load and store buses
  • Fast hardware execution of a high percentage of operations on normalized data resulting in higher overall performance while providing full IEEE 754 standard support when required
  • Divide and square root operations in parallel with other arithmetic operations to reduce the impact of long-latency operations
  • Near IEEE 754 standard compatibility in RunFast mode without support code assistance, providing determinable run-time calculations for all input data
  • Low power consumption, small die size, and reduced kernel code.
Debug Interface ARM9 processors contains hardware extensions for advanced debugging features to facilitate application software and operating system development.
The debug extensions enable halted system debug to examine the internal state of the processor and the external state of the AHB while all other system activity continues as normal.
Monitor debug-mode operation is also supported which enables users to debug the processor while critical interrupt service routines are executing. The debug monitor program typically communicates with the debug host over the debug communication channel.
ETM Interface CoreSight ETM9 provides non intrusive, cycle accurate instruction trace and data trace for ARM9 family processors

System Development

Connect to standard System IP - AMBA® interconnect compatibility for fast and efficient system design with peripherals and memories.

 

System IP

System IP components are essential for building complex system on chips and by utilizing ARM System IP components developers can significantly reduce development and validation cycles, saving cost and reducing time to market

Description

AMBA Bus

System IP Components

Enable fast configuration of embedded systems with an AMBA AHB interface

AHB

AMBA Design Kit (ADK)

AHB Memory Controllers (Dynamic, static and hybrid memory controllers)

AHB

PL24X family

Synthesisable UART

AHB

PL011

Synthesisable Single-wire Peripheral Interface (SPI) controller

AHB

PL022

Synthesisable keyboard or mouse interface complying with IBM-defined PS/2 interface standard

AHB

PL050

Synthesisable GPIO controller supporting 8 bits with interrupt control.

AHB

PL061

 

Media Processors

The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.

Mali-55 GPU

The Mali-55 GPU is the world’s smallest OpenGL ES 1.1 compliant GPU using the Mali tile-based rendering architecture to maximize the efficiency of energy usage in displaying graphical images and to minimize the bandwidth demands on the system.

 

Physical IP

ARM® Physical IP Platforms deliver process optimized IP, for best-in-class implementations of ARM processors.

Standard Cell Logic Libraries

Available in a variety of different architectures ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area

Memory Compilers and Registers

A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.

Interface Libraires

A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces are optimized to deliver high data throughput performance with low pin counts.

 

Tools Ecosystem

All ARM processors are supported by the ARM RealView® portfolio of development tools, as well as a wide range of third party tools, operating system and EDA vendors. ARM RealView tools are unique in their ability to provide solutions that span the complete development process from concept to final product deployment.

 


 
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