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ARM11MPCore Processor

ARM11MPCore Processor Image (View Larger ARM11MPCore Processor Image)
The ARM11™ MPCore™ multicore processor implements the ARM11 microarchitecture and brings multicore scalability with 1 to 4 cores from a single RTL base, enabling simple system design with a single macro to integrate with up to 4x the performance of a single core. The ARM11 MPCore processor brings efficient coherency using built-in SCU, and supported by a wide range of OS with ARM SMP capability. The processor extends the ARMv6 architecture with PIPT caches, supporting 16KB-64KB L1 caches efficiently.
 


ARM11 MPCore: Scalability and power/performance

Why do Multicore?

  • Massive aggregate performance
    • 2.0 Coremarks/MHz per core from ARM11 MPCore
    • Predictable single-thread performance compared with MT cores
    • High power efficiency (DMIPS/mW) & area efficiency
  • Ideally suited to many compute intensive applications:
    • Mixture of network traffic and compute (e.g. STB, WLAN)
    • OS GUI environments with multiple processes (e.g. netbook)
    • Specially written multi-worker data processing applications (e.g. printer)
  • Simple, well-understood ‘SMP’ or ‘AMP’ programming models with uniform 4 GB physical memory makes processor power accessible

Why ARM11 MPcore?

  • ARM11 low dynamic power consumption
    • Proportional to work done (no dynamic power when core in standby WFI)
  • Lowest standby power (static power)
    • OS can easily power off unused cores for very lowest leakage => Efficiency
  • Maturity
    • Derived from popular ARM11 microarchitecture
    • Widely licensed and implemented
    • ARM SMP well supported by OS vendors

 


High Speed Single Core and Area-Optimized Dual Core

PPA Estimates Speed optimized ARM11MP single core Area optimized ARM11MP dual core
Process Geometry 65G OD 65LP
Performance 1075 DMIPS 530 x 2 DMIPS
Performance 1730 Coremarks 854 x 2 Coremarks
Frequency* 865 MHz 427 MHz
Total area 1.77 mm2 3.26 mm2
Power efficiency** 4.1 DMIPS/mW 3.9 * 2 DMIPS/mW

Speed optimized ARM11 MPcore 32/32K L1, Jazelle®, no VFP Dual ARM11MPcore 32/32K L1, Advantage 10T libraries, 2x AXI, Jazelle, no VFP

High speed single core and Area-Optimized dual Core


PPA Estimates ARM11MP 2 core ARM11MP 4 core
Process Geometry 65G 65G
Performance 938 x 2 DMIPS 915 x 4 DMIPS
Performance 3004 Coremarks 5856 Coremarks
Frequency* 751 MHz 732 MHz
Total area 3.9 mm2 8.6 mm2

ARM11MP with VFP+Jazelle+ETM per core, 16/16K L1, dual-AXI, 32 interrupts, 12T Advantage-HS

* at SS, Vdd - 10%, 125C, W/C, 50ps clock jitter, +/- 3% duty cycle, 10% OCV and 100ps hold margin, rcworst parasitics, 12T SC, fast memories, dependent up tools, flows, Physical IP

** Power at TT, Vdd, 25C, measured running Dhrystone


ARM11MPcore
Architecture ARMv6
Dhrystone Performance 1.25 DMIPS / MHz
Multicore
  • 1-4 cores
  • Single core version also available

ISA Support

Memory Management Memory Management Unit
Debug & Trace CoreSight Design Kit

Key Features

ARM11 MPCore Delivers Scalable Multiprocessing

  • Scalability from 1 to 4 Cores
    • RTL synthesis configurations to define scalability between 1 and 4 CPUs
    • Built in interrupt distributor for low latency inter-processor communications
    • Snoop control unit for high performance and power efficient cache coherency
  • Looks like a uniprocessor
    • Simplified SoC integration
    • Common solution for a range of devices
    • Standardized software platform
  • Synthesis configurability
    • Number of processors (1-4)
    • Number of I/O interrupts (32-224)
    • Number of AXI buses (1 or 2)
    • Size of data and inst caches: 16, 32, 64
    • Vector Floating Point coprocessor per CPU
    • Jazelle-DBX option per CPU
    • ETM option per CPU
    • Support for DVFS (auto shifters/latches) similar to ARM1176
    • Synchronous or Asynchronous bus interface
  • Sophisticated power management
    • Support for DVFS of whole MPCore subsystem
    • Dynamic power is controlled by WFI / WFE instructions
      • Stops clock; only leakage
    • To address static power, cores can be powered off to save leakage power
      • N processor system can power off N-1 processors
      • Linux fully supports 'CPU hotplugging'
      • Powering off involves cache cleaning
      • Powering on requires warm boot sequence
    • MPCore supports the powering down of up to 10 core logic and ram blocks independently
      • 4 power domains for each CPU's logic cells
      • 4 power domains for each CPU's caches and RAMS
      • 1 power domain for SCU tag RAMS
      • 1 power domain for remain logic
        • SCU and private peripherals

Cortex Alternative

The Cortex™-A5 processor is a related follow-on product to the ARM11MPCore. The Cortex-A5 processor offers similar speed to ARM11™ processors, at lower power and smaller die area, with the ARMv7 benefits of NEON™, and TrustZone®, as well as a more advanced AMBA® AXI™ bus. The Cortex-A5 also offers 1-4way SMP scalability, extending on the coherent multi-core architecture of ARM11MPCore. Cutting edge new SoC designs for are starting now based on the ARM Cortex-A9 processor for high performance or the Cortex-A5 processor for low power and area with ARMv7 compatibility, however some SoC designs are still starting with ARM11MPCore processor where cost and minimal risk are important considerations.

System IP

The ARM11MPCore processor is commonly integrated with many other IP blocks to optimize the SoC for power and performance.

System IP components are essential for building complex system on chips and by utilizing ARM system IP components developers can significantly reduce development and validation cycles, saving cost and reducing time to market


Description AMBA Bus System IP Component
AMBA 3 Interconnect IP AXI NIC-301, PL301
DMA Controller AXI DMA-330, PL330
Level 2 Cache Controller AXI L2C-310, PL310
Dynamic Memory Controller AXI DMC-340, PL34x
DDR2 Dynamic Memory Controller AXI DMC-341, PL341
Static Memory Controller AXI SMC-35x, PL35x
CoreSight Design Kit ATB CDK-11

Media Processors
The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.
Mali-400 GPU World's first OpenGL ES 2.0 conformant multi-core GPU provides 2D and 3D acceleration with performance scalable up to 1080p resolution
Mali-200 GPU High performance graphical processor providing advanced 2D and 3D acceleration. Supports OpenGL ES 2.0
Mali-55 GPU Small area Open GL ES 1.0 capable GPU

Physical IP
ARM® Physical IP Platforms deliver process optimized IP, for best-in-class processor implementations of the ARM11MPCore at 65 nm and below.
Standard Cell Logic Libraries Available in a variety of different architectures ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area
Memory Compilers and Registers A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.
Interface Libraries A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces are optimized to deliver high data throughput performance with low pin counts.
Process Nodes for ARM11
  • TSMC 65 nm Technology
  • GLOBALFOUNDRIES 65 nm Technology
  • TSMC 40 nm Technology

Tools Support

The ARM RealView® portfolio of development tools, as well as a wide range of third party tools, operating system and EDA vendors supports all ARM processors. ARM RealView tools are unique in their ability to provide solutions that span the complete development process from concept to final product deployment.


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