The ARM® standard cell library product family of Artisan® Physical IP, is developed using the ARM Process-Perfect™ Design Methodology and is based on feedback from customers, EDA, IP, design services and foundry partners. The result is a widely-used set of libraries that offer a wide range of performance and density choices. - AdvantageTM and SAGE-XTM libraries offer an optimal mix of density and speed well suited for mainstream applications
- Advantage-HS and SAGE-HS high-speed libraries complement the mainstream libraries by offering solutions for performance critical designs
- MetroTM libraries are optimized for high-density, low-power applications
- ARM Power Management Kits to actively reduce dynamic and leakage power in standard cell blocks
Each product is delivered with a complete set of views and models for leading EDA tools. ARM standard cell libraries are production proven to minimize development and production risk.
Browse the ARM Physical IP Product Catalog to view the standard cell libraries and other products available for a particular foundry and process. The standard cell libraries’ features and benefits are listed below.
| Features | Benefits | - Optimized for speed and density
- Broad range of drive sizes and functions
- Complex arithmetic and register file cells
- Multiple scan flip-flop choices
- Support for leading EDA tools
- Threshold voltage implant options
| - Optimal performance, area and power balance for mainstream designs
- Minimized static and leakage power for required performance
- Optimize static power through mix/match of cells with different voltage implant options
|
| Features | Benefits | - Optimized for high speed
- Broad range of drive sizes and functions
- Complex arithmetic and register file cells
- Multiple scan flip-flop choices
- Support for leading EDA tools
- Threshold voltage implant options
| - Meet high performance targets in demanding applications
- Optimize chip core area through mix of Advantage-HS blocks with area optimized Metro or Advantage library blocks
- Quickly synthesize and close timing on complex designs
|
| Features | Benefits | - Optimized for density and low power
- Broad range of drive sizes and functions
- Multiple scan flip-flop choices
- Threshold voltage implant options
| - Minimize chip area for performance uncritical designs
- Low dynamic and static power
- Optimize chip core area through mix of Metro blocks and higher performance Advantage or Advantage-HS blocks
- Optimize static power through mix/match of cells with different voltage implant options
|
| Features | Benefits | - Dynamic and leakage power management functions
- Up, down and bidirectional level shifters
- On-chip power gates
- Retention flip-flops
- Back-bias compatible well-tap cells
- Threshold voltage implant options and mixed implant cell design
- Compliments Metro, Advantage and Advantage-HS standard cell libraries
| - Meet high performance targets in demanding applications
- Optimize chip core area through mix of Advantage-HS blocks with area optimized Metro or Advantage library blocks
- Quickly synthesize and close timing on complex designs
|
How to Download ARM Standard Cell LibrariesExisting Customers - Click the Login button above.
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New Customers - Click the Login button above.
- Click on the 'New User' link to register as a new user.
- From Services: My Account page, submit a request.
ARM will review your application. Approved applicants will receive download instructions by email. | 
