ARM Logic IP solutions include a broad array of Standard Cell Libraries coupled with Power Management Kit and ECO Kit extensions delivering optimal performance, power and area when building ARM Processors, Graphics and Fabric IP along with general SoC subsystem implementation. Designed to deliver highest yield thru extensive DFM optimization, ARM Logic solutions make the ideal choice for today’s advanced, deep submicron SoC designs.

Logic IP Features

• Ultra High Density, Balanced and High Speed architectures
• Exceeds foundry DFM (Design For Manufacturability) requirements resulting in highest yields
• High, Regular and Low Vt solutions enabling performance, power and area optimization
• Multi-Channel logic architecture extends the optimization range far beyond Vt-only solutions resulting in 2X leakage power decrease
• Low voltage corners enable voltage island support and further dynamic power reductions
• Temperature inversion corners included to ensure real-world timing accuracy
• Industry leading EDA views and models result in Time To Market advantage and lower costs
• Power Management Kit extension libraries provide optimal solutions for power management across the SoC
• ECO (Engineering Change Order) Kit enables metal only errata fix or new feature implementation

Logic IP Benefits

• Optimal logic solutions for ARM Processors, GPU and Fabric IP ensuring best implementation and optimal performance
• Higher margins delivered thru smaller die area, lower power and high yields
• Time To Market advantage leveraging broadest EDA views, silicon proven technology and manufacturing flexibility
• Lowest risk solutions with more ARM physical IP designs in production than all 3rd party IP providers combined

Power Management Kit

Power Management Kit extension libraries minimize power consumption delivering optimal performance for applications requiring absolute minimal power consumption

• Dynamically operate functional blocks at multiple voltages to achieve optimal tradeoffs
• Level shifters supporting multiple voltage islands
• Power gates and isolation cells enabling sleep mode for leakage savings
• Data retention flip-flops and always-on cells for fast wake-up
• Biasing cells for leakage control
• Pitch matched to High-Density and High-Speed cells
• Available in multiple thresholds
• Available in multiple channel lengths
• Support for industry-standard EDA low-power flows

ECO Kit

ECO Kit extension libraries enable cost effective errata fixing or last minute feature additions at metal

• Base array filler cells
• Metal programmable macros
• Combinational, sequential, and support cells
• Multiple drive strengths
• Characterized for multiple optimization points including temperature inversion