ARM Interface IP provides General Purpose I/O and Specialty I/O completing the Processor to Pads IP required to implement ARM Processors, Graphics, Fabric IP and general SoC applications. Based on ARM’s silicon proven ESD methodology, these Interface IP deliver a robust reliability without compromising any yield for most deep submicron process technologies.

Interface IP Features

• Fully Programmable architecture enabling various operating modes
• Adjustable slew rates
• Programmable drive strengths of 2, 4, 8, and 12mA
• Various termination options
• Support for Fail-Safe and Tolerant Voltage applications
• Compliance to JEDEC Reliability Standards

  • Electrostatic Discharge (ESD)
    • HBM – 2KV
    • MM – 200V
    • CDM – 500V
  • Latch Up (LU)
    • +/- 100mA @ 125C

• Physical design
  • Supports flip-chip and wire-bond packaging

Intefrace IP Benefits

• Interface IP completes the Processor to Pads solutions for ARM Processors, GPU and Fabric IP ensuring flexibility in implementation and optimal performance
• Higher margins delivered thru smaller die area, lower power and high yields
• Time To Market advantage leveraging broadest EDA views, silicon proven technology and manufacturing flexibility
• Lowest risk solutions with more ARM physical IP designs in production than all 3rd party IP providers combined