Standard Cell Libraries

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Available in a variety of different architectures ARM® Standard Cell Libraries support a wide performance range, for all types of SoC designs. Designers can choose between different standard cell library types and optimize their designs for speed, power and/or area. Architectures that fulfill and surpass foundry DFM requirements ensure high manufacturability and yield for all types of applications.

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ARM Artisan Standard Cell Libraries are available from the latest advanced 10nm to established mainstream 250nm. These are "best in class" libraries based on architectural analysis by experts in leading-edge processes and design styles. The libraries include models for successful implementation across the entire design flow, from synthesis to tapeout. ARM processors and other IP use the ARM Standard Cell Libraries for reference and benchmark designs.

Wide performance range for all types of designs

  • Ultra high density/low power, 6 or 7-track (SC6/SC7) libraries for cost critical applications
  • High density/low power, 8 or 9-track (SC8/SC9) libraries for mainstream applications
  • High performance, 10 or 12-track (SC10/SC12) libraries for speed critical designs

Footprint compatible multi-channel length (MC) and multi-Vt libraries

  • MC libraries enable the combination of high performance with ultra-low power
  • MC leakage reduction proven in silicon
  • MC libraries provide higher yield than competing solutions
  • Available for different performance ranges
  • Use multi-Vt flow for MC libraries; no special design flow

ARM has a successful history of library development and takes the forefront in cooperation with foundries, customers and EDA vendors. Such alignment, across key disciplines within the industry, results in continuous improvements in cell sets, architecture and modeling, all of which are proven in thousands of designs.

ARM Standard Cell Libraries are for use in ultra-low power designs in the MHz range up to multiple GHz in performance critical applications. 
  • Variety of architectures based on different track heights and cell designs cover a wide performance, power and area range
    • High Performance libraries are 20% faster than High Density mainstream libraries
    • Ultra High Density versions based on smallest cell height require 20% less area and power than mainstream libraries
  • All libraries are silicon tested at various voltage and temperature conditions and correlated with library models
    • Low voltage Si verification ensures functionality at low power applications

Very large cell set to ensure optimal implementation of all types of design

  • Over 1500 Cells / Vt for FinFET processes
  • Smaller cell set in more mature technologies
  • Wide variety of specialty cells like clock gating cells and decoupling capacitors

Optimized cell set targeted performance range/applications

  • Hand tuned and handcrafted cell designs for highest density and routeability 
  • Multiple beta (P:N) transistor ratios for performance - power tuning
  • Tapless cell design for all libraries at 65nm and smaller geometries as well as for selected 180 to 90 nm libraries
  • 65nm and larger geometries use M1 power rails
  • 45nm and smaller geometries use M2 power rails for optimal support of restricted design rules
  • Strain optimized layouts for high performance libraries in selected process nodes

Leading edge design flow and model support

  • CCS timing, noise and power, ECSM, Voltage Storm, Celtic, AOCV and other specialty models
  • Latest DRC rules and electrical models  

Extensive set of PVT corners

  • Multi-Vdd characterization
  • Overdrive voltage support
  • Support for temperature inversion corners
  • High leakage corner (standard at 90 nm and below)
  • Custom PVT support

ARM Standard Cell Library Logic IP may be used in complex SoC designs thatrequire many types of IP across the design. In addition to Standard Cell Library IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.

Visit DesignStart to find ARM IP solutions for your SoC and start designing today.

ARM Physical IP ARM Processor IP ARM System IP ARM Multimedia IP

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The ARM Processor Selector provides an extensive overview about performance, area and power numbers for a variety of ARM processors and process nodes and types

For some ARM processors specialized Standard Cell Libraries and other optimized Physical IP are available.

The wide performance range of ARM Standard Cell Libraries and the extensive support of different process options and nodes enables designers to target an optimal implementation of all ARM Processors, Multimedia and System IP. The following table gives some guidelines for IP selections. 

ARM IP Standard Cell Library 
Cortex-A Series 12-track High Performance Libraries
9-track High Density Libraries for FinFET processes
Cortex-R Series 9- and 10-track High Density Librarie
Cortex-M Series 6-, 7-, and 8-track Ultra High Density Libraries
Multimedia IP 9- and 10-track High Density Libraries
7- and 8-track Ultra High Density Libraries for FinFET processes
System IP - Interconnect 9- and 10-track High Density Libraries
System IP - Memory Controller 12-track High Performance Libraries

You can view ARM Standard Cell Libraries and other Physical IP products in DesignStart. Registered users of DesignStart can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes. Start your design today with DesignStart!

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