Standard Cell Libraries

• Variety of architectures based on different track heights and cell designs cover a wide performance, power and area range
  • High Performance libraries are 20% faster than High Density mainstream libraries
  • Ultra High Density versions based on smallest cell height require 20% less area and power than mainstream libraries

• All libraries are silicon tested at various voltage and temperature conditions and correlated with library models
  • Low voltage Si verification ensures functionality at low power applications

Very large cell set to ensure optimal implementation of all types of design

• 1250 cells per Vt or channel length at 32/45 nm
• Smaller cell set in more mature technologies
• Wide variety of specialty cells like clock gating cells and decoupling capacitors

Optimized cell set targeted performance range/applications

• Hand tuned and handcrafted cell designs for highest density and routeability 
• Multiple beta (P:N) transistor ratios for performance - power tuning
• Tapless cell design for all libraries at 65nm and smaller geometries as well as for selected 180 to 90 nm libraries
• 65nm and larger geometries use M1 power rails
• 45nm and smaller geometries use M2 power rails for optimal support of restricted design rules
• Strain optimized layouts for high performance libraries in selected process nodes

Leading edge design flow and model support

• CCS timing, noise and power, ECSM, Voltage Storm, Celtic and other specialty models 
• Latest DRC rules and electrical models  

Extensive set of PVT corners

• Multi-Vdd characterization
• Overdrive voltage support
• Support for temperature inversion corners
• High leakage corner (standard at 90 nm and below)
• Custom PVT support

The ARM Processor Selector provides an extensive overview about performance, area and power numbers for a variety of ARM processors and process nodes and types

For some ARM processors specialized Standard Cell Libraries and other optimized Physical IP are available:

The wide performance range of ARM Standard Cell Libraries and the extensive support of different process options and nodes enables designers to target an optimal implementation of all ARM Processors, Multimedia and System IP. The following table gives some guidelines for IP selections. 

Product Briefs

• Common Platform 32nm LP Physical IP Brochure
• TSMC 40nm G Physical IP Brochure
• GLOBALFOUNDRIES 65LPe Physical IP Brochure
• TSMC 180ULL Physical IP Brochure